Datasheet

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 
SPRS161K − MARCH 2001 − REVISED JULY 2007
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
serial communications interface (SCI) module (continued)
Internal
Clock
WUT
Frame Format and Mode
Even/Odd Enable
Parity
SCI RX Interrupt
BRKDT
SCICTL1.1
RXRDY
SCIRXST.6
SCICTL1.3
External
Connections
8
SCICTL2.1
RX/BK INT ENA
SCIRXD
SCIRXST.1
TXENA
SCI TX Interrupt
TX EMPTY
TXRDY
SCICTL2.0
TX INT ENA
SCITXD
RXENA
SCIRXD
RXWAKE
SCICTL1.0
SCICTL1.6
RX ERR INT ENA
TXWAKE
SCITXD
TXINT
SCICCR.6 SCICCR.5
SCITXBUF.7−0
SCIHBAUD. 15−8
Baud Rate
MSbyte
Register
SCILBAUD. 7−0
SCIRXBUF.7−0
Receiver-Data
Buffer
Register
SCIRXST.7
PEFE OE
RX Error
RX Error
SCIRXST.4−2
Transmitter-Data
Buffer Register
8
SCICTL2.6
SCICTL2.7
Baud Rate
LSbyte
Register
RXSHF
Register
TXSHF
Register
SCIRXST.5
RXINT
1
SCIPRI.5
SCIPRI.6
SCI Priority Level
Level 5 Int.
Level 1 Int.
Level 5 Int.
Level 1 Int.
1
0
1
0
SCI TX
Priority
SCI RX
Priority
Figure 16. Serial Communications Interface (SCI) Module Block Diagram