Datasheet

 
 
SPRS161K − MARCH 2001 − REVISED JULY 2007
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
functional block diagram of the 2401A DSP CPU
32
16
Data Bus
16
OSCALE (0−7)
16
1616
32
32
ACCL(16)ACCH(16)C
32
CALU(32)
3232
MUX
ISCALE (0−16)
16
MUX
PREG(32)
Multiplier
TREG0(16)
MUX
16
16
MUX
B1 (256 × 16)
B2 (32 × 16)
DARAM
B0 (256 × 16)
DARAM
7
LSB
from
IR
MUX
DP(9)
9
9
MUX
1616
ARAU(16)
16
3
3
3
3
ARB(3)
ARP(3)
Program Bus
16
16
AR7(16)
AR6(16)
AR5(16)
AR3(16)
AR2(16)
AR1(16)
AR0(16)
Stack 8 × 16
PC
MUX
16
XTAL2
CLKOUT
XTAL1
RS
XF
Control
Data Bus
Program Bus
Data Bus
AR4(16)
16
Data/Prog
16
PSCALE (−6,ā 0,ā 1,ā 4)
16
Data
32
16
16
FLASH EEPROM
MUX
MUX
NPAR
PAR MSTACK
Program Control
(PCTRL)
Memory Map
Register
IMR (16)
IFR (16)
GREG (16)
16
Program Bus
2
XINT[1−2]
NOTES: A. See Table 4 for symbol descriptions.
B. For clarity, the data and program buses are shown as single buses although they include address and data bits.
C. Refer to the TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) for CPU
instruction set information.