Datasheet
SPRS161K − MARCH 2001 − REVISED JULY 2007
24
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interrupt request structure
Table 3. TMS320Lx2401A Interrupt Source Priority and Vectors
INTERRUPT
NAME
OVERALL
PRIORITY
CPU
INTERRUPT
AND
VECTOR
ADDRESS
BIT
POSITION IN
PIRQRx AND
PIACKRx
PERIPHERAL
INTERRUPT
VECTOR
(PIV)
MASK-
ABLE?
SOURCE
PERIPHERAL
MODULE
DESCRIPTION
Reset 1
RSN
0000h
N/A N
RS pin,
Watchdog
Reset from pin, watchdog
timeout
Reserved 2
−
0026h
N/A N CPU Emulator trap
NMI 3
NMI
0024h
N/A N
Nonmaskable
Interrupt
Nonmaskable interrupt,
software interrupt only
PDPINTA 4 0.0 0020h Y EVA
Power device protection
interrupt pin
ADCINT 6
0.1 0004h Y ADC
ADC interrupt in
high-priority mode
XINT1 7
INT1
0.2 0001h Y
External
Interrupt Logic
External interrupt pins in high
XINT2 8
INT1
0002h
0.3 0011h Y
External
Interrupt Logic
External interrupt pins in high
priority
RXINT 10 0.5 0006h Y SCI
SCI receiver interrupt in
high-priority mode
TXINT 11 0.6 0007h Y SCI
SCI transmitter interrupt in
high-priority mode
CMP1INT 14 0.9 0021h Y EVA Compare 1 interrupt
CMP2INT 15 0.10 0022h Y EVA Compare 2 interrupt
CMP3INT 16
INT2
0.11 0023h Y EVA Compare 3 interrupt
T1PINT 17
INT2
0004h
0.12 0027h Y EVA Timer 1 period interrupt
T1CINT 18
0004h
0.13 0028h Y EVA Timer 1 compare interrupt
T1UFINT 19 0.14 0029h Y EVA Timer 1 underflow interrupt
T1OFINT 20 0.15 002Ah Y EVA Timer 1 overflow interrupt
T2PINT 28 1.0 002Bh Y EVA Timer 2 period interrupt
T2CINT 29
INT3
1.1 002Ch Y EVA Timer 2 compare interrupt
T2UFINT 30
INT3
0006h
1.2 002Dh Y EVA Timer 2 underflow interrupt
T2OFINT 31
0006h
1.3 002Eh Y EVA Timer 2 overflow interrupt
CAP1INT 36
INT4
0008h
1.4 0033h Y EVA Capture 1 interrupt
RXINT 43
INT5
1.8 0006h Y SCI
SCI receiver interrupt
(low-priority mode)
TXINT 44
INT5
000Ah
1.9 0007h Y SCI
SCI transmitter interrupt
(low-priority mode)
†
Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information.
NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.