Datasheet

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SPRS161K − MARCH 2001 − REVISED JULY 2007
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
device reset and interrupts (continued)
CPU
IACK
Addr BusData Bus
IRQ GEN
Level 6
IRQ GEN
Level 4
IRQ GEN
Level 3
IRQ GEN
Level 2
IRQ GEN
Level 1
ADCINT
RXINT
CAP1INT
T2OFINT
T2UFINT
T2CINT
T2PINT
T1OFINT
T1UFINT
T1CINT
T1PINT
CMP3INT
CMP2INT
CMP1INT
TXINT
RXINT
ADCINT
INT1
INT2
INT3
INT4
INT6
INT5
IMR
IFR
PIE
PDPINTA
Interrupt from external interrupt pin. The remaining interrupts are internal to the peripherals.
TXINT IRQ GEN
Level 5
XINT2
XINT1
XINT2
XINT1
PIVR & Logic
PIRQR#
PIACK#
Figure 12. Peripheral Interrupt Expansion (PIE) Module Block Diagram for Hardware-Generated Interrupts