Datasheet
SPRS161K − MARCH 2001 − REVISED JULY 2007
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device reset and interrupts
The TMS320Lx2401A software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The Lx2401A recognizes three types
of interrupt sources.
D Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
The Lx2401A devices have two sources of reset: an external reset pin and a watchdog timer time-out
(reset).
D Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two
types:
− External interrupts are generated by one of three external pins corresponding to the interrupts XINT1,
XINT2, and PDPINTA. These three can be masked both by dedicated enable bits and by the CPU
interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core.
− Peripheral interrupts are initiated internally by these on-chip peripheral modules: event manager A,
SCI, and ADC. They can be masked both by enable bits for each event in each peripheral and by the
CPU IMR, which can mask each maskable interrupt line at the DSP core.
D Software-generated interrupts for the Lx2401A devices include:
− The INTR instruction. This instruction allows initialization of any Lx2401A interrupt with software. Its
operand indicates the interrupt vector location to which the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).
− The NMI instruction. This instruction forces a branch to interrupt vector location 24h. This instruction
globally disables maskable interrupts. Lx2401A devices do not have the NMI hardware signal, only
software activation is provided.
− The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The
TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.
− An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction.
Six core interrupts (INT1−INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to
the F24x devices. The PIE manages all the peripheral interrupts from the Lx2401A peripherals and are grouped
to share the six core level interrupts. Figure 12 shows the PIE block diagram for hardware-generated interrupts.
The PIE block diagram (Figure 12) and the interrupt table (Table 3) explain the grouping and interrupt vector
maps. Lx2401A devices have interrupts identical to those of the F24x devices. See Table 3 for details.