Datasheet
SPRS161K − MARCH 2001 − REVISED JULY 2007
17
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constraints while emulating with JTAG port pins and GPIO functions
This section highlights the constraints that are encountered if the emulation/debugging tool attempts to use the
multiplexed JTAG/GPIO pins in their JTAG configuration while the application attempts to use them in the GPIO
configuration at the same time:
1. Since the emulation/debugging tools need complete control of the JTAG port pins, the GPIO functions that
are multiplexed with the JTAG port pins cannot be used when the JTAG pod is connected to the JTAG
header.
2. Applications using the JTAG port pins for its GPIO function must provide some isolation mechanism (such
as jumpers) to isolate the external circuitry associated with the GPIO circuits. This will ensure that the GPIO
circuit does not conflict with the signals from the JTAG pod. To reiterate, the circuitry associated with the
GPIO pins must be isolated from the DSP before the JTAG pod is connected to the JTAG header.
3. It is recommended that the Lx2401A application software does not enable GPIO function for the multiplexed
JTAG/GPIO pins if emulation tools are ever planned to be used concurrently. This will avoid drive conflicts
between JTAG pod signals and GPIO signals—particularly on TCK, TDI and TMS pins. Table 2 shows the
configuration of the multiplexed JTAG/GPIO pins depending on the status of the TRST
pin.
Table 2. Configuration of Multiplexed JTAG/GPIO Pins
TRST = 1 TRST = 0
TCK (signal from the JTAG pod) Can be configured as IOPB1
TDI (signal from the JTAG pod) Can be configured as OPB5
TMS (signal from the JTAG pod) Can be configured as XF
4. TRST pin is internally pulled down. When this pin is left unconnected, it puts the multiplexed JTAG/GPIO
pins in their GPIO configuration. If TRST
is driven high, it puts the multiplexed JTAG/GPIO pins in their JTAG
configuration and the device enters emulation mode. All the emulation and flash programming tools use the
JTAG port and will drive this pin high. TRST
pin controls the functionality of the multiplexed JTAG/GPIO pins.