Datasheet

 
 
SPRS161K − MARCH 2001 − REVISED JULY 2007
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
terminal functions (continued)
NOTE: The multiplexing diagrams are functional representations of the multiplexing scheme. They do not
represent the actual circuit elements within the silicon.
0
1
1
0
MCRA.k
PADATDIR.n
[IOPAn − input data]
PADATDIR.m
(Direction)
FCOMPOE
[COMCONA.9]
PADATDIR.n
[IOPAn − Output Data]
PWMn
PWMn/IOPAn Pin
Pullup
MCRA.k PWMn/IOPAn DIRECTION BIT DATA BIT
MCRA.1 PWM1/IOPA1 PADATDIR.9 PADATDIR.1
MCRA.2 PWM2/IOPA2 PADATDIR.10 PADATDIR.2
MCRA.3 PWM3/IOPA3 PADATDIR.11 PADATDIR.3
MCRA.4 PWM4/IOPA4 PADATDIR.12 PADATDIR.4
MCRA.5 PWM5/IOPA5 PADATDIR.13 PADATDIR.5
MCRA.6 PWM6/IOPA6 PADATDIR.14 PADATDIR.6
Figure 1. PWMn/IOPAn Pin Multiplexing Functional Block Diagram
PADATDIR.0
[IOPA0 − Input Data]
PADATDIR.0
[IOPA0 − Output Data]
PDPINTA
PDPINTA/IOPA0 Pin
MCRA.0 PADATDIR.8
Input
Qualifier
Circuit
EVAIMRA.0
Pullup
Figure 2. PDPINTA/IOPA0 Pin Multiplexing Functional Block Diagram