Datasheet

 
 
SPRS161K − MARCH 2001 − REVISED JULY 2007
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
terminal functions (continued)
Terminal Functions
†
(Continued)
TERMINAL
DESCRIPTION
NAME NO.
DESCRIPTION
TRST 20
JTAG test reset. The function of the TCK, TDI, TDO, and TMS pins depend on the state of the TRST
pin. If TRST = 1 (Test or Debugging mode), the function of these pins will be JTAG function (the GPIO
function of these pins is not available). If TRST
= 0 (Functional mode), these pins function as GPIO. (↓)
NOTE: Do not use pullup resistors on TRST
; it has an internal pulldown device. TRST is an active high
test pin and must be maintained low at all times during normal device operation. In a low-noise
environment, TRST
may be left floating. In other instances, an external pulldown resistor is highly
recommended. The value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is
application-specific, it is recommended that each target board be validated for proper operation of the
debugger and the application.
XTAL1/CLKIN 6 Crystal/Clock input to PLL
XTAL2 7 Crystal output
V
CCP
¶
26
Flash programming voltage pin. This pin must be connected to a 5-V supply for Flash programming. The
Flash cannot be programmed if this pin is connected to GND. When not programming the Flash (i.e.,
during normal device operation), this pin can either be left connected to the 5-V supply or it can be tied
to GND. This pin must not be left floating at any time. Do not use any current-limiting resistor in series
with the 5-V supply on this pin. This pin is a “no connect” (NC) on ROM parts (i.e., this pin is not connected
to any circuitry internal to the device). Connecting this pin to 5 V or leaving it open makes no difference
on ROM parts.
V
DD
5 Core supply (3.3 V)
V
DD
25 Core supply (3.3 V)
V
SS
8 Core ground
V
SS
21 Core ground
V
SS
30 Core ground
†
Bold face type indicates function of the device pin after reset.
‡
It is highly recommended that V
CCA
be isolated from the digital supply voltage (and V
SSA
from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
§
TDI is MUXed with digital output, not digital I/O.
¶
Pin 26 is V
CCP
on LF2401A and is a No Connect (NC) on LC2401A.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±20 µA.)
NOTE: On the target hardware, pins 13 and 14 (EMU0/EMU1) of the JTAG header must be pulled high.
NOTE:
The I/O pins that are MUXed with the JTAG function cannot be used while debugging, since the
emulator needs complete control of the JTAG pins. While debugging, there should not be any
circuitry connected on these MUXed pins that could disturb the JTAG debug process.