SPRS161K − MARCH 2001 − REVISED JULY 2007 D High-Performance Static CMOS Technology D D D D − 25-ns Instruction Cycle Time (40 MHz) − 40-MIPS Performance − Low-Power 3.
SPRS161K − MARCH 2001 − REVISED JULY 2007 Table of Contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 TMS320x240xA device summary . . . . . . . . . . . . . . . 4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TMS320x240xA device summary . . . . . . . . . . . . . . . 5 functional block diagram of the LF2401A DSP controller . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPRS161K − MARCH 2001 − REVISED JULY 2007 REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS161J device-specific data sheet to make it an SPRS161K revision.
SPRS161K − MARCH 2001 − REVISED JULY 2007 description The TMS320Lx2401A† device, a new member of the TMS320C24x generation of digital signal processor (DSP) controllers, is part of the TMS320C2000 platform of fixed-point DSPs. The Lx2401A device offers the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities.
SPRS161K − MARCH 2001 − REVISED JULY 2007 TMS320x240xA device summary Table 1. Device Feature Comparison Between Lx2401A and Lx2402A FEATURE LF2401A LC2401A LF2402A LC2402A C2xx DSP Core Yes Yes Yes Yes Instruction Cycle 25 ns 25 ns 25 ns 25 ns MIPS (40 MHz) 40 MIPS 40 MIPS 40 MIPS 40 MIPS Dual-Access RAM (DARAM) 544 544 544 544 Single-Access RAM (SARAM) 512 512 512 — 8K — 8K — 4K/4K — 4K/4K — RAM (16-bit word) 3.
SPRS161K − MARCH 2001 − REVISED JULY 2007 functional block diagram of the LF2401A DSP controller VDD (3.
SPRS161K − MARCH 2001 − REVISED JULY 2007 functional block diagram of the LC2401A DSP controller VDD (3.
SPRS161K − MARCH 2001 − REVISED JULY 2007 20 19 ADCIN00 21 VSSA 22 VCCA XINT2/ADCSOC/CAP1/IOPA7 /CLKOUT 23 TRST TDO/ IOPB2 24 VSS TDI/ OPB5 32-PIN VF PACKAGE (TOP VIEW) 18 17 VDD 25 16 ADCIN01 VCCP† 26 15 ADCIN02 PWM1/IOPA1 27 14 ADCIN03 PWM2/IOPA2 28 13 ADCIN04 PWM3/IOPA3 29 12 PWM6/IOPA6 VSS 30 11 PWM5/IOPA5 T2PWM/XINT1/IOPB0 31 10 PWM4/IOPA4 PDPINTA/IOPA0 32 6 7 8 XTAL2 VSS SCITXD/ IOPB3 5 XTAL1/CLKIN SCIRXD/ IO
SPRS161K − MARCH 2001 − REVISED JULY 2007 terminal functions Terminal Functions† TERMINAL NAME DESCRIPTION NO. Device Reset (in) and Watchdog Reset (out). RS 9 Device reset. RS causes the device to terminate execution and to set PC = 0. When RS is brought to a high level, execution begins at location 0x0000 of program memory. This pin is driven low by the DSP when a watchdog reset occurs.
SPRS161K − MARCH 2001 − REVISED JULY 2007 terminal functions (continued) Terminal Functions† (Continued) TERMINAL NAME DESCRIPTION NO. ADCIN00 17 Analog input channel 0 ADCIN01 16 Analog input channel 1 ADCIN02 15 Analog input channel 2 ADCIN03 14 Analog input channel 3 ADCIN04 13 Analog input channel 4 VCCA VSSA 19 Analog supply voltage for ADC (3.3 V)‡ Internally connected to VREFHI 18 Analog ground reference for ADC.
SPRS161K − MARCH 2001 − REVISED JULY 2007 terminal functions (continued) Terminal Functions† (Continued) TERMINAL NAME DESCRIPTION NO. JTAG test reset. The function of the TCK, TDI, TDO, and TMS pins depend on the state of the TRST pin. If TRST = 1 (Test or Debugging mode), the function of these pins will be JTAG function (the GPIO function of these pins is not available). If TRST = 0 (Functional mode), these pins function as GPIO.
SPRS161K − MARCH 2001 − REVISED JULY 2007 terminal functions (continued) NOTE: The multiplexing diagrams are functional representations of the multiplexing scheme. They do not represent the actual circuit elements within the silicon. PADATDIR.n [IOPAn − input data] PADATDIR.m (Direction) 0 FCOMPOE [COMCONA.9] 1 Pullup PWMn/IOPAn Pin MCRA.k PADATDIR.n [IOPAn − Output Data] 0 PWMn 1 MCRA.k PWMn/IOPAn DIRECTION BIT DATA BIT MCRA.1 PWM1/IOPA1 PADATDIR.
SPRS161K − MARCH 2001 − REVISED JULY 2007 terminal functions (continued) 1 1 PADATDIR.7 [IOPA7 − Input Data] 0 XINT2 and XINT2 LPM1 Wakeup Logic Input Qualifier Circuit XINT2CR.0 CAP1 CAPCONA[14,13] Pullup XINT2/ADCSOC/ CAP1/IOPA7/ CLKOUT Pin ADSOC ADCTRL2.7 MCRA.7 PADATDIR.15 (Direction) CLKOUT 1 PADATDIR.7 [IOPA7 − Output Data] 0 Figure 3.
SPRS161K − MARCH 2001 − REVISED JULY 2007 terminal functions (continued) PBDATDIR.0 [IOPB0 − Input Data] XINT1CR.0 XINT1 and XINT1 LPM1 Wakeup Logic Input Qualifier Circuit Pullup T2PWM/XINT1/IOPB0 Pin PBDATDIR.8 (Direction Bit) 0 TCOMPOE [GPTCONA.6] 1 MCRA.8 PBDATDIR.0 [IOPB0 − Output Data] 0 T2PWM [PWM Signal] 1 Figure 4. T2PWM/XINT1/IOPB0 Pin Multiplexing Functional Block Diagram PBDATDIR.3 [IOPB3 − Input Data] PBDATDIR.
SPRS161K − MARCH 2001 − REVISED JULY 2007 terminal functions (continued) SCIRXD PBDATDIR.4 [IOPB4 − Input Data] Pullup PBDATDIR.12 (Direction Bit) SCIRXD/IOPB4 Pin MCRA.12 PBDATDIR.4 [IOPB4 − Output Data] Figure 6.
SPRS161K − MARCH 2001 − REVISED JULY 2007 terminal functions (continued) TCK Pullup PBDATDIR.1 [IOPB1 − Input Data] PBDATDIR.1 [IOPB1 − Output Data] TCK/IOPB1 Pin TRST To CPU RS PBDATDIR.9 (Direction Bit) Pullup TDI TDI/OPB5 Pin PBDATDIR.5 [OPB5 − Output Data] TRST RS PBDATDIR.13 (Direction Bit) IOPBDATDIR.2 [IOPB2 − Input Data] TDO/IOPB2 Pin PBDATDIR.2 [IOPB2 − Output Data] 0 TDO 1 Pulldown TRST RS PBDATDIR.
SPRS161K − MARCH 2001 − REVISED JULY 2007 constraints while emulating with JTAG port pins and GPIO functions This section highlights the constraints that are encountered if the emulation/debugging tool attempts to use the multiplexed JTAG/GPIO pins in their JTAG configuration while the application attempts to use them in the GPIO configuration at the same time: 1.
SPRS161K − MARCH 2001 − REVISED JULY 2007 in-circuit emulation options The GPIO functionality of the JTAG/GPIO pins cannot be used when the JTAG function is used for debugging. In applications which require full emulation, it is easy to build an in-circuit emulation system using a 2407A EVM (or any TMS320LF240x target board). This requires some additional planning in the Lx2401A target board design.
SPRS161K − MARCH 2001 − REVISED JULY 2007 memory map Hex 0000 0FFF 1000 1FFF 2000 Hex 0000 Program FLASH SECTOR 0 (4K) Interrupt Vectors (0000−003Fh) Reserved † (0040−0043h) User code begins at 0044h ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ FLASH SECTOR 1 (4K) Reserve
SPRS161K − MARCH 2001 − REVISED JULY 2007 memory map (continued) Hex 0000 1FBF 1FCO ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ 1FFF 2000 Reserved Reserved 7FFF 8000 81FF 8200 87FF 8800 SARAM (512 words) Internal (PON = 1) Reserved (PON = 0) Re
SPRS161K − MARCH 2001 − REVISED JULY 2007 peripheral memory map Interrupt-Mask Register Hex 0000 0003 0004 Reserved 0005 Interrupt Flag Register 0006 0007 Reserved Emulation Registers and Reserved Hex 0000 005F 0060 007F 0080 00FF 0100 Memory-Mapped Registers and Reserved ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ On-Chip DARAM B2 Illegal Reserved 01FF 0200 On-Chip DARAM B0 02FF 0300 03FF 0400 On-Chip DARAM B1 ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ
SPRS161K − MARCH 2001 − REVISED JULY 2007 device reset and interrupts The TMS320Lx2401A software-programmable interrupt structure supports flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The Lx2401A recognizes three types of interrupt sources. D Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any other executing functions.
SPRS161K − MARCH 2001 − REVISED JULY 2007 device reset and interrupts (continued) PIE IMR PDPINTA IFR ADCINT RXINT TXINT Level 1 IRQ GEN INT1 XINT1 XINT2 INT2 CMP1INT CMP2INT CMP3INT T1PINT T1CINT T1UFINT T1OFINT Level 2 IRQ GEN CPU INT3 T2PINT T2CINT T2UFINT T2OFINT Level 3 IRQ GEN INT4 CAP1INT Level 4 IRQ GEN RXINT TXINT Level 5 IRQ GEN ADCINT XINT1 INT5 INT6 Level 6 IRQ GEN IACK XINT2 PIVR & Logic PIRQR# PIACK# Data Bus Addr Bus Interrupt fro
SPRS161K − MARCH 2001 − REVISED JULY 2007 interrupt request structure Table 3. TMS320Lx2401A Interrupt Source Priority and Vectors OVERALL PRIORITY CPU INTERRUPT AND VECTOR ADDRESS Reset 1 Reserved PERIPHERAL INTERRUPT VECTOR (PIV) MASKABLE? SOURCE PERIPHERAL MODULE RSN 0000h N/A N RS pin, Watchdog Reset from timeout 2 − 0026h N/A N CPU Emulator trap NMI 3 NMI 0024h N/A N Nonmaskable Interrupt PDPINTA 4 0.
SPRS161K − MARCH 2001 − REVISED JULY 2007 interrupt request structure (continued) Table 3. TMS320Lx2401A Interrupt Source Priority and Vectors (Continued) INTERRUPT NAME OVERALL PRIORITY ADCINT 47 XINT1 48 XINT2 CPU INTERRUPT AND VECTOR ADDRESS BIT POSITION IN PIRQRx AND PIACKRx PERIPHERAL INTERRUPT VECTOR (PIV) MASKABLE? SOURCE PERIPHERAL MODULE 1.12 0004h Y ADC 1.
SPRS161K − MARCH 2001 − REVISED JULY 2007 scan-based emulation TMS320x2xx devices incorporate scan-based emulation logic for code-development and hardwaredevelopment support. Scan-based emulation allows the emulator to control the processor in the system without the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the x2xx by way of the IEEE 1149.1-compatible (JTAG) interface.
SPRS161K − MARCH 2001 − REVISED JULY 2007 functional block diagram of the 2401A DSP CPU Program Bus Data Bus Control XF RS NPAR 16 PC PAR Program Bus MUX XTAL1 CLKOUT XTAL2 MSTACK MUX Stack 8 × 16 XINT[1−2] 2 FLASH EEPROM Program Control (PCTRL) 16 16 16 Data Bus Data Bus 16 16 16 9 3 AR0(16) DP(9) AR1(16) 16 7 LSB from IR 16 16 AR2(16) ARP(3) 16 MUX MUX AR3(16) 3 16 16 9 AR4(16) 3 AR5(16) ARB(3) TREG0(16) AR6(16) Multiplier A
SPRS161K − MARCH 2001 − REVISED JULY 2007 2401A legend for the internal hardware Table 4. Legend for the 2401A DSP CPU Internal Hardware SYMBOL NAME DESCRIPTION ACC Accumulator 32-bit register that stores the results and provides input for subsequent CALU operations.
SPRS161K − MARCH 2001 − REVISED JULY 2007 2401A legend for the internal hardware (continued) Table 4. Legend for the 2401A DSP CPU Internal Hardware (Continued) SYMBOL NAME DESCRIPTION PREG Product Register 32-bit register holds results of 16 × 16 multiply PSCALE Product-Scaling Shifter 0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product.
SPRS161K − MARCH 2001 − REVISED JULY 2007 status and control registers (continued) Table 5. Status Register Field Definitions (Continued) FIELD FUNCTION DP Data memory page pointer. The 9-bit DP register is concatenated with the 7 LSBs of an instruction word to form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions. INTM Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled.
SPRS161K − MARCH 2001 − REVISED JULY 2007 multiplier The TMS320Lx2401A device uses a 16 x 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned) instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated as 2s-complement numbers, and the result is a 32-bit 2s-complement number.
SPRS161K − MARCH 2001 − REVISED JULY 2007 multiplier (continued) The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed data memory location, with the result placed in PREG.
SPRS161K − MARCH 2001 − REVISED JULY 2007 central arithmetic logic unit (continued) The CALU also has an associated carry bit that is set or reset depending on various operations within the device. The carry bit allows more efficient computation of extended-precision products and additions or subtractions. It is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the single-bit shift and rotate instructions.
SPRS161K − MARCH 2001 − REVISED JULY 2007 internal memory The TMS320Lx2401A device is configured with the following memory modules: D D D D D Dual-access random-access memory (DARAM) Single-access random-access memory (SARAM) ROM (LC2401A) Flash (LF2401A) Boot ROM dual-access RAM (DARAM) There are 544 words × 16 bits of DARAM on the 2401A device. The 2401A DARAM allows writes to and reads from the RAM in the same cycle.
SPRS161K − MARCH 2001 − REVISED JULY 2007 boot ROM† Boot ROM is a 256-word ROM mapped in program space 0000h−00FFh. This ROM will be enabled if the BOOT_EN mode is enabled during reset. Boot-enable function is implemented using combinational logic of the TDI, TRST, and RS pins as described below.
SPRS161K − MARCH 2001 − REVISED JULY 2007 Flash/ROM security The 2401A device has a security feature that prevents external access to Flash/ROM memory. This feature is useful in preventing unauthorized duplication of proprietary code resident on the Flash/ROM memory. If access to Flash/ROM contents are desired for debugging purposes, two actions need to be taken: 1. A “dummy” read of locations 40h, 41h, 42h and 43h (of program memory space) is necessary.
SPRS161K − MARCH 2001 − REVISED JULY 2007 PERIPHERALS The integrated peripherals of the TMS320Lx2401A are described in the following subsections: D D D D D D Event-manager module (EVA) Enhanced analog-to-digital converter (ADC) module Serial communications interface (SCI) module PLL-based clock module Digital I/O and shared pin functions Watchdog (WD) timer module event manager module (EVA) The event-manager module includes general-purpose (GP) timers, full-compare
SPRS161K − MARCH 2001 − REVISED JULY 2007 event manager module (EVA) (continued) 2401A DSP Core Data Bus ADDR Bus Reset INT2,3,4 Clock 16 3 16 16 16 16 EV Control Registers and Control Logic ADC Start of Conversion GP Timer 1 Compare GP Timer 1 T1CON[8,9,10] 16 16 CLKOUT (Internal) Prescaler Full-Compare Units 3 SVPWM State Machine PWM1 3 Deadband Units 3 Output Logic PWM6 16 16 GP Timer 2 Compare Output Logic GP Timer 2 T2PWM Prescaler
SPRS161K − MARCH 2001 − REVISED JULY 2007 general-purpose (GP) timers There are two GP timers.
SPRS161K − MARCH 2001 − REVISED JULY 2007 PWM characteristics Characteristics of the PWMs are as follows: D D D D D D D D D 16-bit registers Programmable deadband for the PWM output pairs, from 0 to 12 µs Minimum deadband width of 25 ns Change of the PWM carrier frequency for PWM frequency wobbling as needed Change of the PWM pulse widths within and after each PWM period as needed External-maskable power and drive-protection interrupts Pulse-pattern-generator circui
SPRS161K − MARCH 2001 − REVISED JULY 2007 enhanced analog-to-digital converter (ADC) module A simplified functional block diagram of the ADC module is shown in Figure 15. The ADC module consists of a 10-bit ADC with a built-in sample-and-hold (S / H) circuit.
SPRS161K − MARCH 2001 − REVISED JULY 2007 enhanced analog-to-digital converter (ADC) module (continued) The ADC module in the 2401A has been enhanced to provide flexible interface to the event manager (EVA). The ADC interface is built around a fast, 10-bit ADC module with total conversion time of 500 ns (S/H + conversion). The ADC module has 5 channels to service EVA.
SPRS161K − MARCH 2001 − REVISED JULY 2007 serial communications interface (SCI) module The 2401A device includes a serial communications interface (SCI) module. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits.
SPRS161K − MARCH 2001 − REVISED JULY 2007 serial communications interface (SCI) module (continued) TXWAKE Frame Format and Mode SCICTL1.3 Parity Even/Odd Enable SCICCR.6 SCICCR.5 1 SCITXBUF.7−0 Transmitter-Data Buffer Register SCI TX Interrupt TXRDY TX INT ENA SCICTL2.7 TX EMPTY 8 TXINT SCICTL2.0 External Connections SCICTL2.6 WUT TXENA TXSHF Register SCITXD SCITXD SCICTL1.1 SCIHBAUD. 15 −8 SCI Priority Level 1 Level 5 Int. 0 Level 1 Int.
SPRS161K − MARCH 2001 − REVISED JULY 2007 PLL-based clock module The 2401A has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 3-bit ratio control to select different CPU clock rates. See Figure 17 for the PLL Clock Module Block Diagram and Table 8 for clock rates.
SPRS161K − MARCH 2001 − REVISED JULY 2007 external reference crystal clock option The internal oscillator is enabled by connecting a crystal across the XTAL1/CLKIN and XTAL2 pins as shown in Figure 18a. The crystal should be in fundamental operation and parallel resonant, with an effective series resistance of 30 Ω−150 Ω and draws no more than 1 mW; it should be specified at a load capacitance of 20 pF.
SPRS161K − MARCH 2001 − REVISED JULY 2007 clock domains (continued) Table 9.
SPRS161K − MARCH 2001 − REVISED JULY 2007 digital I/O and shared pin functions The 2401A has up to 13 general-purpose, bidirectional, digital I/O (GPIO) pins—most of which are shared between primary functions and I/O. Most I/O pins of the 2401A are shared with other functions. The digital I/O ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and shared pin functions are controlled using eight 16-bit registers.
SPRS161K − MARCH 2001 − REVISED JULY 2007 digital I/O control registers Table 11 lists the registers available in the digital I/O module. As with other 2401A peripherals, these registers are memory-mapped to the data space. Table 11.
SPRS161K − MARCH 2001 − REVISED JULY 2007 watchdog (WD) timer module (continued) Table 12.
SPRS161K − MARCH 2001 − REVISED JULY 2007 watchdog (WD) timer module (continued) CLKOUT ÷ 512 WDCLK System Reset 6-Bit FreeRunning Counter 3-bit Prescaler PLL CLKIN /64 /32 On-Chip Oscillator or External Clock /16 /8 /4 /2 CLR 000 001 010 011 WDPS WDCR.2 − 0 0 2 1 100 101 110 WDCR.6 WDFLAG WDCR.7 111 WDDIS WDCNTR.7 −0 8-Bit Watchdog Counter One-Cycle Delay CLR Reset Flag Internal Pullup PS/257 RS pin System Reset Request WDKEY.
SPRS161K − MARCH 2001 − REVISED JULY 2007 development support Texas Instruments (TI) offers an extensive line of development tools for the 240x generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
SPRS161K − MARCH 2001 − REVISED JULY 2007 device and development support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS.
SPRS161K − MARCH 2001 − REVISED JULY 2007 device and development support tool nomenclature (continued) TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, VF) and temperature range (for example, A). Figure 20 provides a legend for reading the complete TMS320Lx2401A device name.
SPRS161K − MARCH 2001 − REVISED JULY 2007 documentation support Extensive documentation supports all of the TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s guides for all devices and development support tools; and hardware and software applications.
SPRS161K − MARCH 2001 − REVISED JULY 2007 A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information. Updated information on the TMS320 DSP controllers can be found on the worldwide web at: http://www.ti.com.
SPRS161K − MARCH 2001 − REVISED JULY 2007 LF2401A AND LC2401A ELECTRICAL SPECIFICATIONS DATA This document contains information on products in more than one phase of development. The electrical specifications for the TMS320LF2401A device are Production Data (PD) and those for the TMS320LC2401A device are Product Preview (PP). These electrical specifications are subject to change.
SPRS161K − MARCH 2001 − REVISED JULY 2007 electrical characteristics over recommended operating temperature range (unless otherwise noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage TEST CONDITIONS MIN VDD = 3.0 V, IOH = IOHMAX All outputs at 50 µA TYP MAX UNIT 2.4 V VDDO − 0.2 IOL = IOLMAX 0.
SPRS161K − MARCH 2001 − REVISED JULY 2007 current consumption by power-supply pins over recommended operating temperature range during low-power modes at 40-MHz CLOCKOUT† (LF2401A) PARAMETER IDD MODE Operational Current OPERATING CONDITIONS TEMPERATURE MIN TYP MAX UNIT Clock to all peripherals is enabled. No I/O pins are switching. −40°C to 85°C (A) 60 70 mA −40°C to 125°C (S) 60 90 mA LPM0 ADC module current Clock to all peripherals is enabled.
SPRS161K − MARCH 2001 − REVISED JULY 2007 Current (mA) I DD current consumption graphs 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40 45 CLKOUT Frequency (MHz) Figure 21. LF2401A Typical Current Consumption (With Peripheral Clocks Enabled) reducing current consumption 240x DSPs incorporate a unique method to reduce the device current consumption.
SPRS161K − MARCH 2001 − REVISED JULY 2007 emulator connection without signal buffering for the DSP (continued) 6 inches or less VDD VDD 13 EMU0 14 EMU1 2 TRST 1 TMS 3 TDI 7 TDO 11 TCK 9 DSP EMU0 PD EMU1 TRST GND TMS GND TDI GND TDO GND TCK GND 5 4 6 8 10 12 TCK_RET JTAG Header Figure 22.
SPRS161K − MARCH 2001 − REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics Output Under Test 50 Ω VLOAD CT IOH Where: IOH VLOAD CT = = = −2 mA (all outputs) 1.5 V 50-pF typical load-circuit capacitance Figure 23. Test Load Circuit signal transition levels The data in this section is shown for the 3.3-V version. Note that some of the signals use different reference voltages, see the recommended operating conditions table.
SPRS161K − MARCH 2001 − REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100.
SPRS161K − MARCH 2001 − REVISED JULY 2007 external reference crystal/clock with PLL circuit enabled timing with the PLL circuit enabled PARAMETER MIN Input clock frequency† fx MAX Resonator 4 13 Crystal 4 20 CLKIN 4 20 UNIT MHz † Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum. switching characteristics over recommended operating conditions [H = 0.
SPRS161K − MARCH 2001 − REVISED JULY 2007 RS timing timing requirements for a reset [H = 0.
SPRS161K − MARCH 2001 − REVISED JULY 2007 RS timing (continued) tp tw(RSL2) td(EX) RS CLKIN XTAL1† TDI‡ TDI/OPB5 BOOT_EN CLKOUT§ I/Os Hi-Z Code-Dependent † XTAL1 refers to internal oscillator clock if on-chip oscillator is used. ‡ The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the “TDI/OPB5” phase, this pin functions as TDI (if TRST is high) or OPB5 (if TRST is low).
SPRS161K − MARCH 2001 − REVISED JULY 2007 RS timing (continued) switching characteristics over recommended operating conditions for a reset [H = 0.
SPRS161K − MARCH 2001 − REVISED JULY 2007 low-power mode timing switching characteristics over recommended operating conditions [H = 0.
SPRS161K − MARCH 2001 − REVISED JULY 2007 low-power mode timing (continued) tp td(EX) A0−A15 td(IDLE−OSC) td(IDLE−COH) CLKOUT td(WAKE−OSC) tw(RSL) RESET † In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software. ‡ Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP.
SPRS161K − MARCH 2001 − REVISED JULY 2007 LPM2 wake-up timing switching characteristics over recommended operating conditions (see Figure 33) PARAMETER MIN Delay time, PDPINTA low to PWM td(PDP-PWM)HZ high-impedance state MAX UNIT if bit 6 of SCSR2 = 0 (6 + 1)tc(CO) + 12† ns if bit 6 of SCSR2 = 1 (12+ 1)tc(CO) + 12† ns Delay time, INT low/high to interrupt-vector fetch td(INT) 10tc(CO) + tw(PDP−WAKE) ns † Includes i/p qualifier cycles plus synchronizati
SPRS161K − MARCH 2001 − REVISED JULY 2007 TIMING EVENT MANAGER INTERFACE PWM timing PWM refers to all PWM outputs on EVA. switching characteristics over recommended operating conditions for PWM timing [H = 0.5tc(CO)] (see Figure 34) PARAMETER tw(PWM)† MIN MAX 2H+5 Pulse duration, PWMx output high/low td(PWM)CO Delay time, CLKOUT low to PWMx output switching † PWM outputs may be 100%, 0%, or increments of tc(CO) with respect to the PWM period.
SPRS161K − MARCH 2001 − REVISED JULY 2007 capture timing timing requirements (see Figure 35) MIN tw(CAP) if bit 6 of SCSR2 = 0 6tc(CO) if bit 6 of SCSR2 = 1 12tc(CO) Pulse duration, CAP1 input low/high CLKOUT tw(CAP) CAP1 Figure 35.
SPRS161K − MARCH 2001 − REVISED JULY 2007 interrupt timing INT refers to XINT1, XINT2, and PDPINTA.
SPRS161K − MARCH 2001 − REVISED JULY 2007 general-purpose input/output timing switching characteristics over recommended operating conditions (see Figure 37) PARAMETER MIN MAX 13 UNIT td(GPO)CO tr(GPO) Delay time, CLKOUT low to GPIO low/high All GPIOs 21 ns Rise time, GPIO switching low to high All GPIOs 12 ns tf(GPO) Fall time, GPIO switching high to low All GPIOs 15 ns timing requirements [H = 0.
SPRS161K − MARCH 2001 − REVISED JULY 2007 10-bit analog-to-digital converter (ADC) The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as VCCA and VSSA. The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic circuitry that can be present on VSS and VCC from coupling into the ADC analog stage. All ADC specifications are given with respect to VSSA unless otherwise noted.
SPRS161K − MARCH 2001 − REVISED JULY 2007 internal ADC module timing† (see Figure 39) MIN MAX 33.
SPRS161K − MARCH 2001 − REVISED JULY 2007 Flash parameters @40 MHz CLOCKOUT (LF2401A) PARAMETER MIN TYP MAX UNIT 30 µs Time/4K Sector 130 ms Erase time† Time/4K Sector 350 ms ICCP (VCCP pin current) Indicates the typical/maximum current consumption during the Clear-Erase-Program (C-E-P) cycle Time/Word (16-bit) Clear/Programming time† 5 15 mA † The indicated time does not include the time it takes to load the C-E-P algorithm and the code (to be pr
SPRS161K − MARCH 2001 − REVISED JULY 2007 EV The Event Manager of the Lx2401A has reduced functionality when compared to that of the 240xA family. Following are the important differences: D D D D D There is no QEP unit. There is only one “Capture” input (CAP1). Although Timer 1 is present, there is no compare output pin (T1CMP/T1PWM). There is no provision to feed an external clock to the timers. There is no external direction control pin for the timers.
SPRS161K − MARCH 2001 − REVISED JULY 2007 peripheral register description Table 16 is a collection of all the programmable registers of the Lx2401A and is provided as a quick reference. Table 16.
SPRS161K − MARCH 2001 − REVISED JULY 2007 peripheral register description (continued) Table 16.
SPRS161K − MARCH 2001 − REVISED JULY 2007 peripheral register description (continued) Table 16.
SPRS161K − MARCH 2001 − REVISED JULY 2007 peripheral register description (continued) Table 16.
SPRS161K − MARCH 2001 − REVISED JULY 2007 peripheral register description (continued) Table 16.
SPRS161K − MARCH 2001 − REVISED JULY 2007 peripheral register description (continued) Table 16.
SPRS161K − MARCH 2001 − REVISED JULY 2007 peripheral register description (continued) Table 16.
SPRS161K − MARCH 2001 − REVISED JULY 2007 peripheral register description (continued) Table 16.
SPRS161K − MARCH 2001 − REVISED JULY 2007 MECHANICAL DATA VF (S-PQFP-G32) PLASTIC QUAD FLATPACK 0,45 0,25 0,80 24 0,20 M 17 25 16 32 9 0,13 NOM 1 8 5,60 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°−ā 7° 1,45 1,35 0,75 0,45 Seating Plane 0,10 1,60 MAX 4040172/D 04/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
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