Datasheet

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

SPRS439M –JUNE 2007–REVISED AUGUST 2012

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6-3 Emulator Connection Without Signal Buffering for the DSP ............................................................. 123

6-4 3.3-V Test Load Circuit......................................................................................................... 124

6-5 Clock Timing..................................................................................................................... 127

6-6 Power-on Reset................................................................................................................. 129

6-7 Warm Reset ..................................................................................................................... 130

6-8 Example of Effect of Writing Into PLLCR Register ......................................................................... 131

6-9 General-Purpose Output Timing .............................................................................................. 132

6-10 Sampling Mode ................................................................................................................. 132

6-11 General-Purpose Input Timing ................................................................................................ 133

6-12 IDLE Entry and Exit Timing.................................................................................................... 134

6-13 STANDBY Entry and Exit Timing Diagram .................................................................................. 136

6-14 HALT Wake-Up Using GPIOn................................................................................................. 138

6-15 PWM Hi-Z Characteristics ..................................................................................................... 139

6-16 ADCSOCAO or ADCSOCBO Timing ........................................................................................ 142

6-17 External Interrupt Timing....................................................................................................... 142

6-18 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 145

6-19 SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 147

6-20 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 149

6-21 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 150

6-22 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 154

6-23 Example Read Access ......................................................................................................... 157

6-24 Example Write Access ......................................................................................................... 159

6-25 Example Read With Synchronous XREADY Access ...................................................................... 161

6-26 Example Read With Asynchronous XREADY Access ..................................................................... 162

6-27 Write With Synchronous XREADY Access.................................................................................. 164

6-28 Write With Asynchronous XREADY Access ................................................................................ 165

6-29 External Interface Hold Waveform............................................................................................ 167

6-30 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 168

6-31 ADC Power-Up Control Bit Timing ........................................................................................... 170

6-32 ADC Analog Input Impedance Model ........................................................................................ 171

6-33 Sequential Sampling Mode (Single-Channel) Timing ...................................................................... 172

6-34 Simultaneous Sampling Mode Timing ....................................................................................... 173

6-35 McBSP Receive Timing........................................................................................................ 177

6-36 McBSP Transmit Timing ....................................................................................................... 177

6-37 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 178

6-38 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 179

6-39 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 180

6-40 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 181