Datasheet

ePWM1/../6,HRPWM1/../6,
eCAP1/../6,eQEP1/2
Peripheral
Registers
Bridge
ClockEnables
I/O
Peripheral
Registers
ClockEnables
I/O
eCAN-A/B
/2
Peripheral
Registers
ClockEnables
I/O
SPI-A,SCI-A/B/C
LOSPCP
LSPCLK
System
Control
Register
Bridge
SYSCLKOUT
MemoryBus
C28xCore
GPIO
Mux
ClockEnables
Peripheral
Registers
I/O
McBSP-A/B
LOSPCP
LSPCLK
ClockEnables
Bridge
HISPCP
HSPCLK
DMA
Bus
Result
Registers
Bridge
12-Bit ADC
ADC
Registers
16Channels
DMA
ClockEnables
PeripheralBus
CLKIN
I2C-A
ClockEnables
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439M –JUNE 2007–REVISED AUGUST 2012
3.6 System Control
This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes. Figure 3-8 shows the various clock and reset domains that will be discussed.
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT). See Figure 3-9 for an illustration of how CLKIN is derived.
Figure 3-8. Clock and Reset Domains
NOTE
There is a 2-SYSCLKOUT cycle delay from when the write to the PCLKCR0, PCLKCR1, and
PCLKCR2 registers (enables peripheral clocks) occurs to when the action is valid. This delay
must be taken into account before attempting to access the peripheral configuration
registers.
Copyright © 2007–2012, Texas Instruments Incorporated Functional Overview 57
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Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234
TMS320F28232