Datasheet

INT12
MUX
INT11
INT2
INT1
CPU
(Enable)(Flag)
INTx
INTx.8
PIEIERx(8:1) PIEIFRx(8:1)
MUX
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
From
Peripherals
or
External
Interrupts
(Enable) (Flag)
IER(12:1)IFR(12:1)
Global
Enable
INTM
1
0
PIEACKx
(Enable/Flag)
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012 www.ti.com
Figure 3-7. Multiplexing of Interrupts Using the PIE Block
Table 3-13. PIE Peripheral Interrupts
(1)
PIE INTERRUPTS
CPU INTERRUPTS
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
WAKEINT TINT0 ADCINT SEQ2INT SEQ1INT
INT1 XINT2 XINT1 Reserved
(LPM/WD) (TIMER 0) (ADC) (ADC) (ADC)
EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
INT2 Reserved Reserved
(ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)
EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT
INT3 Reserved Reserved
(ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)
ECAP6_INT ECAP5_INT ECAP4_INT ECAP3_INT ECAP2_INT ECAP1_INT
INT4 Reserved Reserved
(eCAP6) (eCAP5) (eCAP4) (eCAP3) (eCAP2) (eCAP1)
EQEP2_INT EQEP1_INT
INT5 Reserved Reserved Reserved Reserved Reserved Reserved
(eQEP2) (eQEP1)
MXINTA MRINTA MXINTB MRINTB SPITXINTA SPIRXINTA
INT6 Reserved Reserved
(McBSP-A) (McBSP-A) (McBSP-B) (McBSP-B) (SPI-A) (SPI-A)
DINTCH6 DINTCH5 DINTCH4 DINTCH3 DINTCH2 DINTCH1
INT7 Reserved Reserved
(DMA) (DMA) (DMA) (DMA) (DMA) (DMA)
SCITXINTC SCIRXINTC I2CINT2A I2CINT1A
INT8 Reserved Reserved Reserved Reserved
(SCI-C) (SCI-C) (I2C-A) (I2C-A)
ECAN1_INTB ECAN0_INTB ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA
INT9
(CAN-B) (CAN-B) (CAN-A) (CAN-A) (SCI-B) (SCI-B) (SCI-A) (SCI-A)
INT10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
INT11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
LUF LVF
INT12 Reserved XINT7 XINT6 XINT5 XINT4 XINT3
(FPU) (FPU)
(1) Out of the 96 possible interrupts, 58 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).
54 Functional Overview Copyright © 2007–2012, Texas Instruments Incorporated
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