Datasheet

InterruptControl
XINT3CR(15:0)
Latch
Mux
GPIOXINT3SEL(4:0)
DMA
XINT3
InterruptControl
XINT4CR(15:0)
Latch
Mux
GPIOXINT4SEL(4:0)
XINT4
InterruptControl
XINT5CR(15:0)
Mux
GPIOXINT5SEL(4:0)
XINT5
InterruptControl
XINT6CR(15:0)
Mux
GPIOXINT6SEL(4:0)
XINT6
InterruptControl
XINT7CR(15:0)
Mux
GPIOXINT7SEL(4:0)
XINT7
DMA
DMA
DMA
DMA
96Interrupts
PIE
INT1
to
INT12
C28
Core
GPIO32.int
GPIO63.int
GPIO
Mux
Latch
Latch
Latch
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439M –JUNE 2007–REVISED AUGUST 2012
Figure 3-6. External Interrupts
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with
8 interrupts per group equals 96 possible interrupts. On the 2833x/2823x devices, 58 of these are used by
peripherals as shown in Table 3-13.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.
Copyright © 2007–2012, Texas Instruments Incorporated Functional Overview 53
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TMS320F28232