Datasheet
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012
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Table 2-3. Signal Descriptions (continued)
PIN NO.
PGF,
NAME DESCRIPTION
(1)
ZHH ZJZ
PTP
BALL # BALL #
PIN #
CLOCK
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half
the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 18:16
(XTIMCLK) and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT =
XCLKOUT 138 C11 A10
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF]
to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state
during a reset. (O/Z, 8 mA drive).
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this
XCLKIN 105 J14 G13 case, the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.9-V
oscillator is used to feed clock to X1 pin), this pin must be tied to GND. (I)
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a
ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the
X1 104 J13 G14 1.9-V core digital power supply. A 1.9-V external oscillator may be connected to the X1 pin.
In this case, the XCLKIN pin must be connected to ground. If a 3.3-V external oscillator is
used with the XCLKIN pin, X1 must be tied to GND. (I)
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected
X2 102 J11 H14
across X1 and X2. If X2 is not used, it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the
address contained at the location 0x3FFFC0. When XRS is brought to a high level,
execution begins at the location pointed to by the PC. This pin is driven low by the DSC
XRS 80 L10 M13
when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the
watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑)
The output buffer of this pin is an open-drain with an internal pullup. It is recommended
that this pin be driven by an open-drain device.
ADC SIGNALS
ADCINA7 35 K4 K1 ADC Group A, Channel 7 input (I)
ADCINA6 36 J5 K2 ADC Group A, Channel 6 input (I)
ADCINA5 37 L1 L1 ADC Group A, Channel 5 input (I)
ADCINA4 38 L2 L2 ADC Group A, Channel 4 input (I)
ADCINA3 39 L3 L3 ADC Group A, Channel 3 input (I)
ADCINA2 40 M1 M1 ADC Group A, Channel 2 input (I)
ADCINA1 41 N1 M2 ADC Group A, Channel 1 input (I)
ADCINA0 42 M3 M3 ADC Group A, Channel 0 input (I)
ADCINB7 53 K5 N6 ADC Group B, Channel 7 input (I)
ADCINB6 52 P4 M6 ADC Group B, Channel 6 input (I)
ADCINB5 51 N4 N5 ADC Group B, Channel 5 input (I)
ADCINB4 50 M4 M5 ADC Group B, Channel 4 input (I)
ADCINB3 49 L4 N4 ADC Group B, Channel 3 input (I)
ADCINB2 48 P3 M4 ADC Group B, Channel 2 input (I)
ADCINB1 47 N3 N3 ADC Group B, Channel 1 input (I)
ADCINB0 46 P2 P3 ADC Group B, Channel 0 input (I)
ADCLO 43 M2 N2 Low Reference (connect to analog ground) (I)
ADCRESEXT 57 M5 P6 ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
ADCREFIN 54 L5 P7 External reference input (I)
24 Introduction Copyright © 2007–2012, Texas Instruments Incorporated
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