Datasheet

M51
M50
M47
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
DR
M44
M48
M49
M43
LSB
MSB
M52
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012 www.ti.com
Table 6-61. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
M49 t
su(DRV-CKXH)
Setup time, DR valid before CLKX high 30 8P – 10 ns
M50 t
h(CKXH-DRV)
Hold time, DR valid after CLKX high 1 8P – 10 ns
M51 t
su(FXL-CKXL)
Setup time, FSX low before CLKX low 8P + 10 ns
M52 t
c(CKX)
Cycle time, CLKX 2P
(1)
16P ns
(1) 2P = 1/CLKG
Table 6-62. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
MASTER SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
M43 t
h(CKXH-FXL)
Hold time, FSX low after CLKX high 2P
(1)
ns
M44 t
d(FXL-CKXL)
Delay time, FSX low to CLKX low P ns
M47 t
dis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from 6 6P + 6 ns
FSX high
M48 t
d(FXL-DXV)
Delay time, FSX low to DX valid 6 4P + 6 ns
(1) 2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency
will be LSPCLK/16; that is, 4.6875 MHz and P = 13.3 ns.
Figure 6-39. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
180 Electrical Specifications Copyright © 2007–2012, Texas Instruments Incorporated
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TMS320F28232