Datasheet

XCLKOUT
(1/2 XTIMCLK)
XHOLD
XR/W,
XZCS0
,
XZCS6
,
XZCS7
XD[0:31]XD[15:0]
Valid
XHOLDA
t
d(HL-HiZ)
t
d(HH-HAH)
High-Impedance
XA[19:0]
Valid
Valid
High-Impedance
t
d(HH-BV)
t
d(HL-HAL)
High-Impedance
(A)
(B)
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012 www.ti.com
Table 6-49. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
(1) (2) (3)
MIN MAX UNIT
t
d(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all address, data, and 4t
c(XTIM)
+ t
c(XCO)
+ 30 ns
control
t
d(HL-HAL)
Delay time, XHOLD low to XHOLDA low 4t
c(XTIM)
+ 2t
c(XCO)
+ 30 ns
t
d(HH-HAH)
Delay time, XHOLD high to XHOLDA high 4t
c(XTIM)
+ 30 ns
t
d(HH-BV)
Delay time, XHOLD high to bus valid 6t
c(XTIM)
+ 30 ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of XCLKOUT.
Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value
specified.
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-30. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
168 Electrical Specifications Copyright © 2007–2012, Texas Instruments Incorporated
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