Datasheet

XCLKOUT
(/1 Mode)
XHOLD
XZCS0, XZCS6, XZCS7
XD[31:0], XD[15:0]
Valid
XHOLDA
t
d(HL-Hiz)
t
d(HH-HAH)
High-Impedance
XA[19:0]
Valid
Valid
High-Impedance
t
d(HH-BV)
t
d(HL-HAL)
(A)
(B)
XR/W
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439M –JUNE 2007–REVISED AUGUST 2012
Table 6-48. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
(1) (2)
MIN MAX UNIT
t
d(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all address, data, and control 4t
c(XTIM)
+ 30 ns
t
d(HL-HAL)
Delay time, XHOLD low to XHOLDA low 5t
c(XTIM)
+ 30 ns
t
d(HH-HAH)
Delay time, XHOLD high to XHOLDA high 3t
c(XTIM)
+ 30 ns
t
d(HH-BV)
Delay time, XHOLD high to bus valid 4t
c(XTIM)
+ 30 ns
t
d(HL-HAL)
Delay time, XHOLD low to XHOLDA low 4t
c(XTIM)
+ 2t
c(XCO)
+ 30 ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-29. External Interface Hold Waveform
Copyright © 2007–2012, Texas Instruments Incorporated Electrical Specifications 167
Submit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234
TMS320F28232