Datasheet

TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439M –JUNE 2007–REVISED AUGUST 2012
6.14.8 External Interface Ready-on-Write Timing With One External Wait State
Table 6-45. External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER MIN MAX UNIT
t
d(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low 1 ns
t
d(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high – 1 0.5 ns
t
d(XCOH-XA)
Delay time, XCLKOUT high to address valid 1.5 ns
t
d(XCOHL-XWEL)
Delay time, XCLKOUT high/low to XWE0, XWE1 low
(1)
2 ns
t
d(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE0, XWE1 high
(1)
2 ns
t
d(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low 1 ns
t
d(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high – 1 0.5 ns
t
en(XD)XWEL
Enable time, data bus driven from XWE0, XWE1 low
(1)
0 ns
t
d(XWEL-XD)
Delay time, data valid after XWE0, XWE1 active low
(1)
1 ns
t
h(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(2)
ns
t
h(XD)XWE
Hold time, write data valid after XWE0, XWE1 inactive high
(1)
TW – 2
(3)
ns
t
dis(XD)XRNW
Maximum time for DSP to release the data bus after XR/W inactive high 4 ns
(1) XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
(3) TW = trail period, write access (see Table 6-36)
Table 6-46. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
(1)
MIN MAX UNIT
t
su(XRDYsynchL)XCOHL
Setup time, XREADY (synchronous) low before XCLKOUT high/low 12 ns
t
h(XRDYsynchL)
Hold time, XREADY (synchronous) low 6 ns
t
e(XRDYsynchH)
Earliest time XREADY (synchronous) can go high before the sampling 3 ns
XCLKOUT edge
t
su(XRDYsynchH)XCOHL
Setup time, XREADY (synchronous) high before XCLKOUT high/low 12 ns
t
h(XRDYsynchH)XZCSH
Hold time, XREADY (synchronous) held high after zone chip select high 0 ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-27:
E =(XWRLEAD + XWRACTIVE) t
c(XTIM)
When first sampled, if XREADY (synchronous) is high, then the access will complete. If XREADY (synchronous) is low, it is sampled
again each t
c(XTIM)
until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE +n –1) t
c(XTIM)
– t
su(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-47. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
(1)
MIN MAX UNIT
t
su(XRDYasynchL)XCOHL
Setup time, XREADY (asynchronous) low before XCLKOUT high/low 11 ns
t
h(XRDYasynchL)
Hold time, XREADY (asynchronous) low 6 ns
t
e(XRDYasynchH)
Earliest time XREADY (asynchronous) can go high before the sampling 3 ns
XCLKOUT edge
t
su(XRDYasynchH)XCOHL
Setup time, XREADY (asynchronous) high before XCLKOUT high/low 11 ns
t
h(XRDYasynchH)XZCSH
Hold time, XREADY (asynchronous) held high after zone chip select high 0 ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-27:
E = (XWRLEAD + XWRACTIVE –2) t
c(XTIM)
. When first sampled, if XREADY (asynchronous) is high, then the access will complete. If
XREADY (asynchronous) is low, it is sampled again each t
c(XTIM)
until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE –3 + n) t
c(XTIM)
– t
su(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Copyright © 2007–2012, Texas Instruments Incorporated Electrical Specifications 163
Submit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234
TMS320F28232