Datasheet

TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012 www.ti.com
6.14.6 External Interface Write Timing
Table 6-40. External Interface Write Switching Characteristics
PARAMETER MIN MAX UNIT
t
d(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low 1 ns
t
d(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high –1 0.5 ns
t
d(XCOH-XA)
Delay time, XCLKOUT high to address valid 1.5 ns
t
d(XCOHL-XWEL)
Delay time, XCLKOUT high/low to XWE0, XWE1
(1)
low 2 ns
t
d(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE0, XWE1 high 2 ns
t
d(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low 1 ns
t
d(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high –1 0.5 ns
t
en(XD)XWEL
Enable time, data bus driven from XWE0, XWE1 low 0 ns
t
d(XWEL-XD)
Delay time, data valid after XWE0, XWE1 active low 1 ns
t
h(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(2)
ns
t
h(XD)XWE
Hold time, write data valid after XWE0, XWE1 inactive high TW – 2
(3)
ns
t
dis(XD)XRNW
Maximum time for DSP to release the data bus after XR/W inactive high 4 ns
(1) XWE1 is used in 32-bit data bus mode only. In 16-bit mode, this signal is XA0.
(2) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high.
This includes alignment cycles.
(3) TW = Trail period, write access. See Table 6-36.
158 Electrical Specifications Copyright © 2007–2012, Texas Instruments Incorporated
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