Datasheet

Lead
Active
Trail
DIN
t
d(XCOHL-XRDL)
t
d(XCOH-XA)
t
d(XCOH-XZCSL)
t
d(XCOHL-XRDH)
t
h(XD)XRD
t
d(XCOHL-XZCSH)
XCLKOUT=XTIMCLK
XCLKOUT=1/2XTIMCLK
XZCS0XZCS6XZCS7, ,
XA[0:19]
XRD
XWE0XWE1,
(D)
XR/W
XD[0:31],XD[0:15]
t
su(XD)XRD
t
a(A)
t
a(XRD)
XREADY
(E)
(A)(B)
(C)
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439M –JUNE 2007–REVISED AUGUST 2012
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which
remains high.
D. XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-23. Example Read Access
XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE
≥ 1 ≥ 0 ≥ 0 0 0 N/A
(1)
N/A
(1)
N/A
(1)
N/A
(1)
(1) N/A = Not applicable (or “Don’t care”) for this example
Copyright © 2007–2012, Texas Instruments Incorporated Electrical Specifications 157
Submit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234
TMS320F28232