Datasheet

TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012 www.ti.com
6.14.5 External Interface Read Timing
Table 6-38. External Interface Read Timing Requirements
MIN MAX UNIT
t
a(A)
Access time, read data from address valid (LR + AR) – 16
(1)
ns
t
a(XRD)
Access time, read data valid from XRD active low AR – 14
(1)
ns
t
su(XD)XRD
Setup time, read data valid before XRD strobe inactive high 14 ns
t
h(XD)XRD
Hold time, read data valid after XRD inactive high 0 ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 6-36.
Table 6-39. External Interface Read Switching Characteristics
PARAMETER MIN MAX UNIT
t
d(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low 1 ns
t
d(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high –1 0.5 ns
t
d(XCOH-XA)
Delay time, XCLKOUT high to address valid 1.5 ns
t
d(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active low 0.5 ns
t
d(XCOHL-XRDH)
Delay time, XCLKOUT high/low to XRD inactive high –1.5 0.5 ns
t
h(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
(1)
ns
t
h(XA)XRD
Hold time, address valid after XRD inactive high
(1)
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
156 Electrical Specifications Copyright © 2007–2012, Texas Instruments Incorporated
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