Datasheet

TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012 www.ti.com
6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:
1 Lead: LR ≥ t
c(XTIM)
LW ≥ t
c(XTIM)
2 Active: AR ≥ 2 × t
c(XTIM)
AW ≥ 2 × t
c(XTIM)
NOTE
Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
≥ 1 ≥ 1 ≥ 0 ≥ 1 ≥ 1 ≥ 0 0, 1
Examples of valid and invalid timing when using synchronous XREADY:
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
Invalid
(1)
0 0 0 0 0 0 0, 1
Invalid
(1)
1 0 0 1 0 0 0, 1
Valid 1 1 0 1 1 0 0, 1
(1) No hardware to detect illegal XTIMING configurations
152 Electrical Specifications Copyright © 2007–2012, Texas Instruments Incorporated
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TMS320F28232