Datasheet

C4
C3
XCLKOUT
(B)
XCLKIN
(A)
C5
C9
C10
C1
C8
C6
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439M –JUNE 2007–REVISED AUGUST 2012
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-5. Clock Timing
6.8 Power Sequencing
No requirements are placed on the power up/down sequence of the various power pins to ensure the
correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers
of the I/O pins are powered prior to the 1.9-V transistors, it is possible for the output buffers to turn on,
causing a glitch to occur on the pin during power up. To avoid this behavior, power the V
DD
pins prior to or
simultaneously with the V
DDIO
pins, ensuring that the V
DD
pins have reached 0.7 V before the V
DDIO
pins
reach 0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for t
w(RSL1)
after the input clock is stable (see Table 6-
11). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 μs prior to V
DD
reaching 1.5 V. This is to
enhance flash reliability.
No voltage larger than a diode drop (0.7 V) above V
DDIO
should be applied to any digital pin (for analog
pins, it is 0.7 V above V
DDA
) prior to powering up the device. Furthermore, V
DDIO
and V
DDA
should always
be within 0.3 V of each other. Voltages applied to pins on an unpowered device can bias internal P-N
junctions in unintended ways and produce unpredictable results.
Copyright © 2007–2012, Texas Instruments Incorporated Electrical Specifications 127
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