Datasheet

CS
A(18:0)
OE
WE
D(15:0)
Low 16-bits
External
wait-state
generator
XREADY
XCLKOUT
XA(19:1)
XRD
XWE0
XD(15:0)
XINTF
CS
A(18:0)
OE
WE
D(31:16)
XA0/
(select )
XWE1
XWE1
XD(31:16)
XZCS0 XZCS6 XZCS7, ,
High 16-bits
CS
A(19:1)
A(0)
OE
WE
D(15:0)
16-bits
External
wait-state
generator
XREADY
XCLKOUT
XA(19:1)
XZCS0 XZCS6 XZCS7, ,
XA0/XWE1
XRD
XWE0
XD(15:0)
XINTF
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com SPRS439M –JUNE 2007–REVISED AUGUST 2012
Figure 4-21. Typical 16-bit Data Bus XINTF Connections
Figure 4-22. Typical 32-bit Data Bus XINTF Connections
Table 4-19. XINTF Configuration and Control Register Mapping
NAME ADDRESS SIZE (x16) DESCRIPTION
XTIMING0 0x00−0B20 2 XINTF Timing Register, Zone 0
XTIMING6
(1)
0x00−0B2C 2 XINTF Timing Register, Zone 6
XTIMING7 0x00−0B2E 2 XINTF Timing Register, Zone 7
XINTCNF2
(2)
0x00−0B34 2 XINTF Configuration Register
XBANK 0x00−0B38 1 XINTF Bank Control Register
XREVISION 0x00−0B3A 1 XINTF Revision Register
XRESET 0x00−0B3D 1 XINTF Reset Register
(1) XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used.
(2) XINTCNF1 is reserved and not currently used.
Copyright © 2007–2012, Texas Instruments Incorporated Peripherals 107
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TMS320F28232