Datasheet
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012
Table 5-16. CLA Control Registers
CLA1 EALLOW
REGISTER NAME SIZE (x16) DESCRIPTION
(1)
ADDRESS PROTECTED
MVECT1 0x1400 1 Yes CLA Interrupt/Task 1 Start Address
MVECT2 0x1401 1 Yes CLA Interrupt/Task 2 Start Address
MVECT3 0x1402 1 Yes CLA Interrupt/Task 3 Start Address
MVECT4 0x1403 1 Yes CLA Interrupt/Task 4 Start Address
MVECT5 0x1404 1 Yes CLA Interrupt/Task 5 Start Address
MVECT6 0x1405 1 Yes CLA Interrupt/Task 6 Start Address
MVECT7 0x1406 1 Yes CLA Interrupt/Task 7 Start Address
MVECT8 0x1407 1 Yes CLA Interrupt/Task 8 Start Address
MCTL 0x1410 1 Yes CLA Control Register
MMEMCFG 0x1411 1 Yes CLA Memory Configure Register
MPISRCSEL1 0x1414 2 Yes Peripheral Interrupt Source Select Register 1
MIFR 0x1420 1 Yes Interrupt Flag Register
MIOVF 0x1421 1 Yes Interrupt Overflow Register
MIFRC 0x1422 1 Yes Interrupt Force Register
MICLR 0x1423 1 Yes Interrupt Clear Register
MICLROVF 0x1424 1 Yes Interrupt Overflow Clear Register
MIER 0x1425 1 Yes Interrupt Enable Register
MIRUN 0x1426 1 Yes Interrupt RUN Register
MIPCTL 0x1427 1 Yes Interrupt Priority Control Register
MPC
(2)
0x1428 1 – CLA Program Counter
MAR0
(2)
0x142A 1 – CLA Aux Register 0
MAR1
(2)
0x142B 1 – CLA Aux Register 1
MSTF
(2)
0x142E 2 – CLA STF Register
MR0
(2)
0x1430 2 – CLA R0H Register
MR1
(2)
0x1434 2 – CLA R1H Register
MR2
(2)
0x1438 2 – CLA R2H Register
MR3
(2)
0x143C 2 – CLA R3H Register
(1) All registers in this table are CSM protected
(2) The main C28x CPU has read only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes
to this register.
Table 5-17. CLA Message RAM
ADDRESS RANGE SIZE (x16) DESCRIPTION
0x1480 – 0x14FF 128 CLA to CPU Message RAM
0x1500 – 0x157F 128 CPU to CLA Message RAM
Copyright © 2010–2012, Texas Instruments Incorporated Peripheral and Electrical Specifications 81
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