Datasheet

t
h(boot-mode)
(A)
t
w(RSL2)
INTOSC1
X1/X2
XRS
Boot-Mode
Pins
XCLKOUT
I/O Pins
Address/Data/
Control
(Internal)
Boot-ROM Execution Starts
User-Code Execution Starts
User-Code Dependent
User-Code Execution Phase
User-Code Dependent
User-Code Execution
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
GPIO Pins as Input
Peripheral/GPIO Function
t
d(EX)
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012
Table 5-7. Reset (XRS) Timing Requirements
MIN MAX UNIT
t
h(boot-mode)
Hold time for boot-mode pins 1000t
c(SCO)
cycles
t
w(RSL2)
Pulse duration, XRS low on warm reset 32t
c(OSCCLK)
cycles
Table 5-8. Reset (XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
t
w(RSL1)
Pulse duration, XRS driven by device 600 μs
t
w(WDRS)
Pulse duration, reset pulse generated by watchdog 512t
c(OSCCLK)
cycles
t
d(EX)
Delay time, address/data valid after XRS high 32t
c(OSCCLK)
cycles
t
INTOSCST
Start up time, internal zero-pin oscillator 3 μs
t
OSCST
(1)
On-chip crystal-oscillator start-up time 1 10 ms
(1) Dependent on crystal/resonator and board design.
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 5-5. Warm Reset
Copyright © 2010–2012, Texas Instruments Incorporated Peripheral and Electrical Specifications 67
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TMS320F28064 TMS320F28063 TMS320F28062