Datasheet

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012

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2.9.4 USB and HRCAP PLL Module (PLL2)

In addition to the main system PLL, these devices also contain a second PLL (PLL2) which can be used to

clock the USB and HRCAP peripherals. The PLL supports multipliers of 1 to 15 and has a fixed divide-by-

two on its output.

PLL2 may be clocked from the following three sources by modifying the PLL2CLKSRCSEL bits

appropriately in the PLL2CTL register:

• INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1 and provides a 10-

MHz clock. If used as a clock source for HRCAP, the oscillator compensation routine should be called

frequently. Because of accuracy requirements, INTOSC1 cannot be used as a clock source for the

USB.

• Crystal/Resonator Operation: The (crystal) oscillator enables the use of an external crystal or resonator

attached to the device to provide the time base. The crystal or resonator is connected to the X1/X2

pins.

• External Clock Source Operation: This mode allows the reference clock to be derived from an external

single-ended clock source connected to either GPIO19 or GPIO38. The XCLKINSEL bit in the XCLK

NOTE

For proper operation of the USB module, PLL2 should be configured to generate a 120-MHz

clock. This will be divided by two to yield the desired 60 MHz for the USB peripheral.

HRCAP supports a maximum clock input frequency of 120 MHz.

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Product Folder Links: TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

TMS320F28064 TMS320F28063 TMS320F28062