Datasheet

Watchdog
Peripherals
XINT1
Interrupt Control
XINT1
XINT1CR[15:0]
Interrupt Control
XINT2
XINT2CR[15:0]
GPIO
MUX
WDINT
INT1
to
INT12
NMI
XINT1CTR[15:0]
XINT2CTR[15:0]
XINT3CTR[15:0]
Low-Power Modes
LPMINT
WAKEINT
Sync
SYSCLKOUT
M
U
X
XINT2
M
U
X
XINT3
ADC
XINT2SOC
GPIOXINT1SEL[4:0]
GPIOXINT2SEL[4:0]
M
U
X
Interrupt Control
XINT3
XINT3CR[15:0]
System Control
(See the System Control section.)
INT14
INT13
GPIO0.int
GPIO31.int
DMA
clear
DMA
PIE
Up to 96 Interrupts
DMA
DMA
TOUT1
CPU TIMER 2
CPU TIMER 0
TINT0
CPU TIMER 1
TINT2
TINT1
Flash Wrapper
GPIOXINT3SEL[4:0]
M
U
X
NMI Interrupt With Watchdog Function
(See the NMI Watchdog section.)
NMIRS
GPIO0.int
GPIO31.int
CLOCKFAIL
CPUTMR2CLK
DMA
C28x
Core
(SPI, SCI, McBSP, I2C, eCAN, ePWM, eCAP, eQEP,
HRCAP, ADC, CLA)
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012 www.ti.com
5.8 Interrupts
Figure 5-10 shows how the various interrupt sources are multiplexed.
Figure 5-10. External and PIE Interrupt Sources
74 Peripheral and Electrical Specifications Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062