Datasheet

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012
4.3 Electrical Characteristics
(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
OH
= I
OH
MAX 2.4
V
OH
High-level output voltage V
I
OH
= 50 μA V
DDIO
– 0.2
V
OL
Low-level output voltage I
OL
= I
OL
MAX 0.4 V
All GPIO –80 –140 –205
Pin with pullup
V
DDIO
= 3.3 V, V
IN
= 0 V
enabled
Input current XRS pin –230 –300 –375
I
IL
μA
(low level)
Pin with pulldown
V
DDIO
= 3.3 V, V
IN
= 0 V ±2
enabled
Pin with pullup
V
DDIO
= 3.3 V, V
IN
= V
DDIO
±2
enabled
Input current
I
IH
μA
(high level)
Pin with pulldown
V
DDIO
= 3.3 V, V
IN
= V
DDIO
28 50 80
enabled
Output current, pullup or
I
OZ
V
O
= V
DDIO
or 0 V ±2 μA
pulldown disabled
C
I
Input capacitance 2 pF
V
DDIO
BOR trip point Falling V
DDIO
2.50 2.78 2.96 V
V
DDIO
BOR hysteresis 35 mV
Supervisor reset release delay Time after BOR/POR/OVR event is removed to XRS
400 800 μs
time release
VREG V
DD
output Internal VREG on 1.9 V
(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage
(V
DD
) go out of range.
Copyright © 2010–2012, Texas Instruments Incorporated Device Operating Conditions 61
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TMS320F28064 TMS320F28063 TMS320F28062