Datasheet

I/O Pin
In
Out
DIR (0 = Input, 1 = Output)
(Force Hi-Z When High)
SYSRS
C28
Core
Sync
RS
XRS
PLL
+
Clocking
Logic
MCLKRS
VREGHALT
Deglitch
Filter
On-Chip
Voltage
Regulator
(VREG)
VREGENZ
POR/BOR
Generating
Module
XRS
Pin
SYSCLKOUT
WDRST
(A)
JTAG
TCK
Detect
Logic
PBRS
(B)
Internal
Weak PU
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012
A. WDRST is the reset signal from the CPU-watchdog.
B. PBRS is the reset signal from the POR/BOR module.
Figure 2-10. VREG + POR + BOR + Reset Signal Connectivity
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 45
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TMS320F28064 TMS320F28063 TMS320F28062