Datasheet

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012 www.ti.com
2.8 VREG, BOR, POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip
voltage regulator (VREG) to generate the V
DD
voltage from the V
DDIO
supply. This eliminates the cost and
space of a second external regulator on an application board. Additionally, internal power-on reset (POR)
and brown-out reset (BOR) circuits monitor both the V
DD
and V
DDIO
rails during power-up and run mode.
2.8.1 On-chip Voltage Regulator (VREG)
A linear regulator generates the core voltage (V
DD
) from the V
DDIO
supply. Therefore, although capacitors
are required on each V
DD
pin to stabilize the generated voltage, power need not be supplied to these pins
to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the
primary concern of the application.
2.8.1.1 Using the On-chip VREG
To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended
operating voltage should be supplied to the V
DDIO
and V
DDA
pins. In this case, the V
DD
voltage needed by
the core logic will be generated by the VREG. Each V
DD
pin requires on the order of 1.2 μF (minimum)
capacitance for proper regulation of the VREG. These capacitors should be located as close as possible
to the V
DD
pins.
2.8.1.2 Disabling the On-chip VREG
To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to
the V
DD
pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied
high.
2.8.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the
burden of monitoring the V
DD
and V
DDIO
supply rails from the application board. The purpose of the POR is
to create a clean reset throughout the device during the entire power-up procedure. The trip point is a
looser, lower trip point than the BOR, which watches for dips in the V
DD
or V
DDIO
rail during device
operation. The POR function is present on both V
DD
and V
DDIO
rails at all times. After initial device power-
up, the BOR function is present on V
DDIO
at all times, and on V
DD
when the internal VREG is enabled
(VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below their
respective trip point. Additionally, when the internal voltage regulator is enabled, an over-voltage
protection circuit will tie XRS low if the V
DD
rail rises above its trip point. See Section 4 for the various trip
points as well as the delay time for the device to release the XRS pin after the under-voltage or over-
voltage condition is removed. Figure 2-10 shows the VREG, POR, and BOR. To disable both the V
DD
and
V
DDIO
BOR functions, a bit is provided in the BORCFG register. See the "Systems Control and Interrupts"
chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18) for
details.
44 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062