Datasheet

t
d(IDLE−XCOL)
Wake-up
Signal
(H)
X1/X2 or
XCLKIN
XCLKOUT
Flushing Pipeline
(A)
Device
Status
STANDBY Normal ExecutionSTANDBY
(G)(B)
(C)
(D)(E)
(F)
t
w(WAKE-INT)
t
d(WAKE-STBY)
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012 www.ti.com
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
• 64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the
wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 5-55. STANDBY Entry and Exit Timing Diagram
Table 5-74. HALT Mode Timing Requirements
MIN MAX UNIT
t
w(WAKE-GPIO)
Pulse duration, GPIO wake-up signal t
oscst
+ 2t
c(OSCCLK)
cycles
t
w(WAKE-XRS)
Pulse duration, XRS wakeup signal t
oscst
+ 8t
c(OSCCLK)
cycles
Table 5-75. HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
d(IDLE-XCOL)
Delay time, IDLE instruction executed to XCLKOUT low 32t
c(SCO)
45t
c(SCO)
cycles
t
p
PLL lock-up time 1 ms
Delay time, PLL lock to program execution resume
1125t
c(SCO)
cycles
• Wake up from flash
t
d(WAKE-HALT)
– Flash module in sleep state
35t
c(SCO)
cycles
• Wake up from SARAM
152 Peripheral and Electrical Specifications Copyright © 2010–2012, Texas Instruments Incorporated
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