Datasheet
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584J –APRIL 2009–REVISED OCTOBER 2013
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4.7 Inter-Integrated Circuit (I
2
C)
The device contains one I
2
C Serial Port. Figure 4-11 shows how the I
2
C peripheral module interfaces
within the device.
The I
2
C module has the following features:
• Compliance with the Philips Semiconductors I
2
C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I
2
C Fast-mode rate)
• One 4-word receive FIFO and one 4-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode
For more information on the I
2
C, see the TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C)
Module Reference Guide (literature number SPRUFZ9).
78 Peripherals Copyright © 2009–2013, Texas Instruments Incorporated
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