Datasheet

S
SPICTL.0
SPIINTFLAG
SPIINT
ENA
SPISTS.6
S
Clock
Polarity
Talk
LSPCLK
SPIBitRate
StateControl
Clock
Phase
Receiver
OverrunFlag
SPICTL.4
Overrun
INTENA
SPICCR.3-0
SPIBRR.6-0
SPICCR.6
SPICTL.3
SPIDAT.15-0
SPICTL.1
M
S
M
Master/Slave
SPISTS.7
SPIDAT
DataRegister
M
S
SPICTL.2
SPIChar
SPISIMO
SPISOMI
SPICLK
SW2
S
M
M
S
SW3
ToCPU
M
SW1
RXFIFO_0
RXFIFO_1
-----
RXFIFO_3
TXFIFORegisters
TXFIFO_0
TXFIFO_1
-----
TXFIFO_3
RXFIFORegisters
16
16
16
TXInterrupt
Logic
RXInterrupt
Logic
SPIINT
SPITX
SPIFFOVF
FLAG
SPIFFRX.15
TXFIFOInterrupt
RXFIFOInterrupt
SPIRXBUF
SPITXBUF
SPIFFTX.14
SPIFFENA
SPISTE
16
0
12
3
0
12
3
4
5
6
TW
TW
TW
SPIPRI.0
TRIWIRE
SPIPRI.1
STEINV
STEINV
SPIRXBUF
BufferRegister
SPITXBUF
BufferRegister
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com SPRS584J –APRIL 2009–REVISED OCTOBER 2013
Figure 4-6 is a block diagram of the SPI in slave mode.
A. SPISTE is driven low by the master for a slave device.
Figure 4-6. SPI Module Block Diagram (Slave Mode)
Copyright © 2009–2013, Texas Instruments Incorporated Peripherals 67
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TMS320F28035