Datasheet

56-Pin
64-Pin
80-Pin
VDDA
VDDA
VREFLO
Tied To
VSSA
VSSA
VREFLO
VREFHI
A0
VREFHI
Tied To
A0
A1
A2
A1
A2
A3
A3
A4
A4
A5
A6
A6
A7
A7
B0
B0
B1
B1
B2
B2
B3
B3
B4
B4
B5
B6
B6
B7
B7
(3.3 V) VDDA
(Agnd) VSSA
VREFLO
Diff
Interface Reference
Comp1
VREFHI
A0
B0
AIO2
AIO10
A1
B1
10-Bit
DAC
A2
B2
COMP1OUT
A3
B3
AIO4
AIO12
A4
B4
Comp2
10-Bit
DAC
COMP2OUT
Comp3
10-Bit
DAC
COMP3OUT
ADC
B5
A5
AIO6
AIO14
A6
B6
A7
B7
Simultaneous Sampling Channels
Signal Pinout
Temperature Sensor
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com SPRS584J –APRIL 2009–REVISED OCTOBER 2013
4.2 Analog Block
A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x.
The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the
timing control of start of conversions. Figure 4-2 shows the interaction of the analog module with the rest
of the F2803x system.
For more information on the ADC, see the TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter
(ADC) and Comparator Reference Guide (literature number SPRUGE5).
Figure 4-2. Analog Pin Configurations
Copyright © 2009–2013, Texas Instruments Incorporated Peripherals 59
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