Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (12x12) 32-Bit 60 MHz I/O number 45

TMS320F28030, TMS320F28031, TMS320F28032

TMS320F28033, TMS320F28034, TMS320F28035

www.ti.com

SPRS584J –APRIL 2009–REVISED OCTOBER 2013

3.7.3 PLL-Based Clock Module

The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking

signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control

PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing

to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes

1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of

the PLL (VCOCLK) is at least 50 MHz.

Table 3-18. PLL Settings

SYSCLKOUT (CLKIN)

PLLCR[DIV] VALUE

(1) (2)

PLLSTS[DIVSEL] = 0 or 1

(3)

PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3

0000 (PLL bypass) OSCCLK/4 (Default)

(1)

OSCCLK/2 OSCCLK

0001 (OSCCLK * 1)/4 (OSCCLK * 1)/2 (OSCCLK * 1)/1

0010 (OSCCLK * 2)/4 (OSCCLK * 2)/2 (OSCCLK * 2)/1

0011 (OSCCLK * 3)/4 (OSCCLK * 3)/2 (OSCCLK * 3)/1

0100 (OSCCLK * 4)/4 (OSCCLK * 4)/2 (OSCCLK * 4)/1

0101 (OSCCLK * 5)/4 (OSCCLK * 5)/2 (OSCCLK * 5)/1

0110 (OSCCLK * 6)/4 (OSCCLK * 6)/2 (OSCCLK * 6)/1

0111 (OSCCLK * 7)/4 (OSCCLK * 7)/2 (OSCCLK * 7)/1

1000 (OSCCLK * 8)/4 (OSCCLK * 8)/2 (OSCCLK * 8)/1

1001 (OSCCLK * 9)/4 (OSCCLK * 9)/2 (OSCCLK * 9)/1

1010 (OSCCLK * 10)/4 (OSCCLK * 10)/2 (OSCCLK * 10)/1

1011 (OSCCLK * 11)/4 (OSCCLK * 11)/2 (OSCCLK * 11)/1

1100 (OSCCLK * 12)/4 (OSCCLK * 12)/2 (OSCCLK * 12)/1

(1) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog

reset only. A reset issued by the debugger or the missing clock detect logic has no effect.

(2) This register is EALLOW protected. See the TMS320x2803x Piccolo System Control and Interrupts Reference Guide (literature number

SPRUGL8) for more information.

(3) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the

PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.

Table 3-19. CLKIN Divide Options

PLLSTS [DIVSEL] CLKIN DIVIDE

0 /4

1 /4

2 /2

3 /1

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TMS320F28035