Datasheet

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TMS320F28030, TMS320F28031, TMS320F28032

TMS320F28033, TMS320F28034, TMS320F28035

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SPRS584J –APRIL 2009–REVISED OCTOBER 2013

Table 3-13. PIE MUXed Peripheral Interrupt Vector Table

(1)

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

INT1.y WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1

(LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 – (ADC) (ADC)

0xD4E 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40

INT2.y Reserved EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT

– (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)

0xD5E 0xD5C 0xD5A 0xD58 0xD56 0xD54 0xD52 0xD50

INT3.y Reserved EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT

– (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)

0xD6E 0xD6C 0xD6A 0xD68 0xD66 0xD64 0xD62 0xD60

INT4.y HRCAP2_INT HRCAP1_INT Reserved Reserved Reserved Reserved Reserved ECAP1_INT

(HRCAP2) (HRCAP1) – – – – – (eCAP1)

0xD7E 0xD7C 0xD7A 0xD78 0xD76 0xD74 0xD72 0xD70

INT5.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved EQEP1_INT

– – – – – – – (eQEP1)

0xD8E 0xD8C 0xD8A 0xD88 0xD86 0xD84 0xD82 0xD80

INT6.y Reserved Reserved Reserved Reserved SPITXINTB SPIRXINTB SPITXINTA SPIRXINTA

– – – – (SPI-B) (SPI-B) (SPI-A) (SPI-A)

0xD9E 0xD9C 0xD9A 0xD98 0xD96 0xD94 0xD92 0xD90

INT7.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

– – – – – – – –

0xDAE 0xDAC 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0

INT8.y Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A

– – – – – – (I2C-A) (I2C-A)

0xDBE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0

INT9.y Reserved Reserved ECAN1_INTA ECAN0_INTA LIN1_INTA LIN0_INTA SCITXINTA SCIRXINTA

– – (CAN-A) (CAN-A) (LIN-A) (LIN-A) (SCI-A) (SCI-A)

0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0

INT10.y ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1

(ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC)

0xDDE 0xDDC 0xDDA 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0

INT11.y CLA1_INT8 CLA1_INT7 CLA1_INT6 CLA1_INT5 CLA1_INT4 CLA1_INT3 CLA1_INT2 CLA1_INT1

(CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA)

0xDEE 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0

INT12.y LUF LVF Reserved Reserved Reserved Reserved Reserved XINT3

(CLA) (CLA) – – – – – Ext. Int. 3

0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0

(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be

used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a

peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.

To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

• No peripheral within the group is asserting interrupts.

• No peripheral interrupts are assigned to the group (for example, PIE group 7).

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