Datasheet

CPU TIMER 2
CPU TIMER 0
Watchdog
Peripherals
(SPI, SCI, ePWM, I C, HRPWM, HRCAP,
eCAP, ADC, eQEP, CLA, LIN, eCAN)
2
TINT0
XINT1
Interrupt Control
XINT1
XINT1CR(15:0)
Interrupt Control
XINT2
XINT2CR(15:0)
GPIO
MUX
WDINT
INT1
to
INT12
NMI
XINT2CTR(15:0)
XINT3CTR(15:0)
CPU TIMER 1
TINT2
Low Power Modes
LPMINT
WAKEINT
Sync
SYSCLKOUT
MUX
XINT2
XINT3
ADC
XINT2SOC
GPIOXINT1SEL(4:0)
GPIOXINT2SEL(4:0)
GPIOXINT3SEL(4:0)
Interrupt Control
XINT3
XINT3CR(15:0)
XINT3CTR(15:0)
NMI interrupt with watchdog function
(See the NMI Watchdog section.)
NMIRS
System Control
(See the System
Control section.)
INT14
INT13
GPIO0.int
GPIO31.int
CLOCKFAIL
CPUTMR2CLK
C28
Core
MUX
MUX
TINT1
PIE
Up to 96 Interrupts
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com SPRS584J –APRIL 2009–REVISED OCTOBER 2013
3.5 Interrupts
Figure 3-5 shows how the various interrupt sources are multiplexed.
Figure 3-5. External and PIE Interrupt Sources
Copyright © 2009–2013, Texas Instruments Incorporated Functional Overview 41
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TMS320F28035