Datasheet

TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584J –APRIL 2009–REVISED OCTOBER 2013 www.ti.com
3.3 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 3-8.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 3-9.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 3-10.
Peripheral Frame 3: These are peripherals that are mapped to the 32-bit peripheral bus and are
accessible by the CLA. See Table 3-11.
Table 3-8. Peripheral Frame 0 Registers
(1)
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
(2)
Device Emulation Registers 0x00 0880 – 0x00 0984 261 Yes
System Power Control Registers 0x00 0985 – 0x00 0987 3 Yes
FLASH Registers
(3)
0x00 0A80 – 0x00 0ADF 96 Yes
Code Security Module Registers 0x00 0AE0 – 0x00 0AEF 16 Yes
ADC registers 0x00 0B00 – 0x00 0B0F 16 No
(0 wait read only)
CPU–TIMER0/1/2 Registers 0x00 0C00 – 0x00 0C3F 64 No
PIE Registers 0x00 0CE0 – 0x00 0CFF 32 No
PIE Vector Table 0x00 0D00 – 0x00 0DFF 256 No
CLA Registers 0x00 1400 – 0x00 147F 128 Yes
CLA to CPU Message RAM (CPU writes ignored) 0x00 1480 – 0x00 14FF 128 NA
CPU to CLA Message RAM (CLA writes ignored) 0x00 1500 – 0x00 157F 128 NA
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
Table 3-9. Peripheral Frame 1 Registers
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
eCAN-A registers 0x00 6000 – 0x00 61FF 512
(1)
eCAP1 registers 0x00 6A00 – 0x00 6A1F 32 No
HRCAP1 registers 0x00 6AC0 – 0x00 6ADF 32
(1)
HRCAP2 registers 0x00 6AE0 – 0x00 6AFF 32
(1)
eQEP1 registers 0x00 6B00 – 0x00 6B3F 64
(1)
LIN-A registers 0x00 6C00 – 0x00 6C7F 128
(1)
GPIO registers 0x00 6F80 – 0x00 6FFF 128
(1)
(1) Some registers are EALLOW protected. See the module reference guide for more information.
38 Functional Overview Copyright © 2009–2013, Texas Instruments Incorporated
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