Datasheet

3 External Interrupts
M0
SARAM 1Kx16
(0-wait)
16-bit Peripheral Bus
SPISTEx
M1
SARAM 1Kx16
(0-wait)
eCAN
(32-mail
box)
SCI
(4L FIFO)
ePWM
SPI
(4L FIFO)
I C
2
(4L FIFO)
LIN
HRPWM
32-Bit Peripheral Bus
GPIO MUX
C28x
32-bit CPU
A7:0
B7:0
PIE
CPU Timer 0
CPU Timer 1
CPU Timer 2
TCK
TDI
TMS
TDO
TRST
OSC1,
OSC2,
Ext,
PLL,
LPM,
WD
XCLKIN
X2
XRS
32-bit Peripheral Bus
(CLA accessible)
eCAP
ECA Px
EPW Mx A EPW Mx B
CA NTXx
CANR Xx
SDA x SCL x
SPISIMO x SPISOMIx
SPIC LK x
COMP1OUT
SCIR XDx
GPIO
Mux
LPM Wakeup
CLA
ADC
Boot-ROM
8Kx16
(0-wait)
SARAM
4K/6K/
8K x 16
(CLA Only on
28033 and 28035)
(0-wait)
Secure
L INA RX
LI NAT X
COMP
COMP1A
COMP1B
COMP2A
COMP2B
COMP3A
COMP3B
COMP2OUT
COMP3OUT
eQEP
32-bit peripheral bus
(CLA-accessible)
EQ EPxA EQ EPxB
EQE PxI
EQEPxS
SCIT XD x
X1
GPIO
MUX
AIO
MUX
From
COMP1OUT,
COMP2OUT,
COMP3OUT
VREG
POR/
BOR
Memory Bus
CLA Bus
Memory Bus
Memory Bus
TZx
PSWD
FLASH
16K/32K/64K x 16
Secure
OTP/Flash
Wrapper
OTP 1K x 16
Secure
Code
Security
Module
HRCAP
HRCAPx
EPWMSYNCI
EPWMSYNCO
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com SPRS584J –APRIL 2009–REVISED OCTOBER 2013
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram for the device.
A. Not all peripheral pins are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
1.5 Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For more
detail on each of these steps, see the following:
• Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0).
• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)
• TMS320F28x MCU Development and Experimenter's Kits (http://www.ti.com/f28xkits)
Copyright © 2009–2013, Texas Instruments Incorporated TMS320F2803x (Piccolo) MCUs 3
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