Datasheet
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com
SPRS584J –APRIL 2009–REVISED OCTOBER 2013
Table 2-2. Terminal Functions
(1)
(continued)
TERMINAL
I/O/Z DESCRIPTION
PN PAG RSH
NAME
PIN # PIN # PIN #
CLOCK
See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the
same frequency, one-half the frequency, or one-fourth the frequency of
SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register.
XCLKOUT See GPIO18 – O/Z
At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by
setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to
XCLKOUT for this signal to propogate to the pin.
See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is
controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default
selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the
X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be
disabled via bit 14 in the CLKCTL register. If a crystal/resonator is used, the
XCLKIN See GPIO19 and GPIO38 I XCLKIN path must be disabled by bit 13 in the CLKCTL register.
NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock
for normal device operation may need to incorporate some hooks to disable this
path during debug using the JTAG connector. This is to prevent contention with
the TCK signal, which is active during JTAG debug sessions. The zero-pin
internal oscillators may be used during this time to clock the device.
On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic
resonator must be connected across X1 and X2. In this case, the XCLKIN path
X1 52 41 36 I
must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must
be tied to GND. (I)
On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be
X2 51 40 35 O
connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in
power-on-reset (POR) and brown-out-reset (BOR) circuitry. As such, no external
circuitry is needed to generate a reset pulse. During a power-on or brown-out
condition, this pin is driven low by the device. See Section 6.3, Electrical
Characteristics, for thresholds of the POR/BOR block. This pin is also driven low
by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin
is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be,
XRS 9 7 5 I/O
an external circuitry may also drive this pin to assert a device reset. In this case, it
is recommended that this pin be driven by an open-drain device. An R-C circuit
must be connected to this pin for noise immunity reasons. Regardless of the
source, a device reset causes the device to terminate execution. The program
counter points to the address contained at the location 0x3FFFC0. When reset is
deactivated, execution begins at the location designated by the program counter.
The output buffer of this pin is an open-drain with an internal pullup. (I/OD)
ADC, COMPARATOR, ANALOG I/O
ADCINA7 11 9 7 I ADC Group A, Channel 7 input
ADCINA6 12 10 8 I ADC Group A, Channel 6 input
COMP3A I Comparator Input 3A
AIO6 I/O Digital AIO 6
ADCINA5 13 – – I ADC Group A, Channel 5 input
ADCINA4 14 11 9 I ADC Group A, Channel 4 input
COMP2A I Comparator Input 2A
AIO4 I/O Digital AIO 4
ADCINA3 15 12 10 I ADC Group A, Channel 3 input
ADCINA2 16 13 11 I ADC Group A, Channel 2 input
COMP1A I Comparator Input 1A
AIO2 I/O Digital AIO 2
Copyright © 2009–2013, Texas Instruments Incorporated Introduction 15
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