Datasheet
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584J –APRIL 2009–REVISED OCTOBER 2013
www.ti.com
Table 6-32. SPI Master Mode External Timing (Clock Phase = 0)
(1)(2)(3)(4)(5)
SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD
SPIBRR = 0 OR 2 AND SPIBRR > 3
NO. UNIT
MIN MAX MIN MAX
1 t
c(SPC)M
Cycle time, SPICLK 4t
c(LCO)
128t
c(LCO)
5t
c(LCO)
127t
c(LCO)
ns
2 t
w(SPCH)M
Pulse duration, SPICLK high 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10 0.5t
c(SPC)M
– 0.5t
c(LCO)
ns
(clock polarity = 0)
t
w(SPCL)M
Pulse duration, SPICLK low 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10 0.5t
c(SPC)M
– 0.5t
c(LCO)
(clock polarity = 1)
3 t
w(SPCL)M
Pulse duration, SPICLK low 0.5t
c(SPC)M
– 10 0.5
tc(SPC)M
0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10 0.5t
c(SPC)M
+ 0.5t
c(LCO)
ns
(clock polarity = 0)
t
w(SPCH)M
Pulse duration, SPICLK high 0.5
tc(SPC)M
– 10 0.5t
c(SPC)M
0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10 0.5t
c(SPC)M
+ 0.5t
c(LCO)
(clock polarity = 1)
4 t
d(SPCH-SIMO)M
Delay time, SPICLK high to SPISIMO 10 10 ns
valid (clock polarity = 0)
t
d(SPCL-SIMO)M
Delay time, SPICLK low to SPISIMO 10 10
valid (clock polarity = 1)
5 t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid after 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10 ns
SPICLK low (clock polarity = 0)
t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid after 0.5t
c(SPC)M
– 10 0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10
SPICLK high (clock polarity = 1)
8 t
su(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK 26 26 ns
low (clock polarity = 0)
t
su(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK 26 26
high (clock polarity = 1)
9 t
v(SPCL-SOMI)M
Valid time, SPISOMI data valid after 0.25t
c(SPC)M
– 10 0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10 ns
SPICLK low (clock polarity = 0)
t
v(SPCH-SOMI)M
Valid time, SPISOMI data valid after 0.25t
c(SPC)M
– 10 0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10
SPICLK high (clock polarity = 1)
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) t
c(SPC)
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) t
c(LCO)
= LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
130 Electrical Specifications Copyright © 2009–2013, Texas Instruments Incorporated
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