Datasheet

TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584J –APRIL 2009–REVISED OCTOBER 2013 www.ti.com
Table 6-15. STANDBY Mode Timing Requirements
TEST CONDITIONS MIN NOM MAX UNIT
Without input qualification 3t
c(OSCCLK)
Pulse duration, external
t
w(WAKE-INT)
cycles
wake-up signal
With input qualification
(1)
(2 + QUALSTDBY) * t
c(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
Table 6-16. STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Delay time, IDLE instruction
t
d(IDLE-XCOL)
32t
c(SCO)
45t
c(SCO)
cycles
executed to XCLKOUT low
Delay time, external wake signal to program execution
cycles
resume
(1)
Without input qualifier 100t
c(SCO)
• Wake up from flash
cycles
– Flash module in active
With input qualifier 100t
c(SCO)
+ t
w(WAKE-INT)
state
t
d(WAKE-STBY)
Without input qualifier 1125t
c(SCO)
• Wake up from flash
cycles
– Flash module in sleep
With input qualifier 1125t
c(SCO)
+ t
w(WAKE-INT)
state
Without input qualifier 100t
c(SCO)
cycles
• Wake up from SARAM
With input qualifier 100t
c(SCO)
+ t
w(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
122 Electrical Specifications Copyright © 2009–2013, Texas Instruments Incorporated
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