Datasheet

TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com SPRS584J –APRIL 2009–REVISED OCTOBER 2013
6.7.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 2803x MCUs. Table 6-3 lists the cycle times of various clocks.
Table 6-3. 2803x Clock Table and Nomenclature (60-MHz Devices)
MIN NOM MAX UNIT
t
c(SCO)
, Cycle time 16.67 500 ns
SYSCLKOUT
Frequency 2 60 MHz
t
c(LCO)
, Cycle time 16.67 66.67
(2)
ns
LSPCLK
(1)
Frequency 15
(2)
60 MHz
t
c(ADCCLK)
, Cycle time 16.67 ns
ADC clock
Frequency 60 MHz
(1) Lower LSPCLK will reduce device power consumption.
(2) This is the default reset value if SYSCLKOUT = 60 MHz.
Table 6-4. Device Clocking Requirements/Characteristics
MIN NOM MAX UNIT
t
c(OSC)
, Cycle time 50 200 ns
On-chip oscillator (X1/X2 pins)
(Crystal/Resonator)
Frequency 5 20 MHz
t
c(CI)
, Cycle time (C8) 33.3 200 ns
External oscillator/clock source
(XCLKIN pin) — PLL Enabled
Frequency 5 30 MHz
t
c(CI)
, Cycle time (C8) 33.33 250 ns
External oscillator/clock source
(XCLKIN pin) — PLL Disabled
Frequency 4 30 MHz
Limp mode SYSCLKOUT
Frequency range 1 to 5 MHz
(with /2 enabled)
t
c(XCO)
, Cycle time (C1) 66.67 2000 ns
XCLKOUT
Frequency 0.5 15 MHz
PLL lock time
(1)
t
p
1 ms
(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are
used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).
Copyright © 2009–2013, Texas Instruments Incorporated Electrical Specifications 113
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