Datasheet

WAKE INT
(A)(B)
XCLKOUT
Address/Data
(internal)
t
d(WAKE−IDLE)
t
w(WAKE−INT)
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013
6.10.4 Low-Power Mode Wakeup Timing
Table 6-17 shows the timing requirements, Table 6-18 shows the switching characteristics, and Figure 6-
14 shows the timing diagram for IDLE mode.
Table 6-17. IDLE Mode Timing Requirements
(1)
MIN NOM MAX UNIT
Without input qualifier 2t
c(SCO)
t
w(WAKE-INT)
Pulse duration, external wake-up signal cycles
With input qualifier 5t
c(SCO)
+ t
w(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-16.
Table 6-18. IDLE Mode Switching Characteristics
(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Delay time, external wake signal to program execution resume
(2)
cycles
Without input qualifier 20t
c(SCO)
cycles
• Wake-up from Flash
– Flash module in active state With input qualifier 20t
c(SCO)
+ t
w(IQSW)
t
d(WAKE-IDLE)
Without input qualifier 1050t
c(SCO)
cycles
• Wake-up from Flash
– Flash module in sleep state With input qualifier 1050t
c(SCO)
+ t
w(IQSW)
Without input qualifier 20t
c(SCO)
cycles
• Wake-up from SARAM
With input qualifier 20t
c(SCO)
+ t
w(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-16.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake-up) signal involves additional latency.
A. WAKE INT can be any enabled interrupt, WDINT or XRS.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 6-14. IDLE Entry and Exit Timing
Copyright © 2008–2013, Texas Instruments Incorporated Electrical Specifications 97
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