Datasheet

GPIO
t
r(GPO)
t
f(GPO)
OSCCLK
SYSCLKOUT
WritetoPLLCR
OSCCLK*2
(CurrentCPU
Frequency)
OSCCLK/2
(CPUfrequencywhilePLL isstabilizing
withthedesiredfrequency.Thisperiod
(PLL lock-uptimet )is1mslong.)
p
OSCCLK*4
(ChangedCPUfrequency)
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013 www.ti.com
Figure 6-9 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.
Figure 6-9. Example of Effect of Writing Into PLLCR Register
6.10 General-Purpose Input/Output (GPIO)
6.10.1 GPIO - Output Timing
Table 6-15. General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
r(GPO)
Rise time, GPIO switching low to high All GPIOs 13
(1)
ns
t
f(GPO)
Fall time, GPIO switching high to low All GPIOs 13
(1)
ns
t
fGPO
Toggling frequency 15 MHz
(1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Table 6-15 are applicable for a 40-pF load on I/O pins.
Figure 6-10. General-Purpose Output Timing
94 Electrical Specifications Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021
TMS320F28020 TMS320F280200