Datasheet

t
h(boot-mode)
(A)
t
w(RSL2)
INTOSC1
X1/X2
XRS
Boot-Mode
Pins
XCLKOUT
I/OPins
Address/Data/
Control
(Internal)
Boot-ROMExecutionStarts
User-CodeExecutionStarts
User-CodeDependent
User-CodeExecutionPhase
User-CodeDependent
User-CodeExecution
Peripheral/GPIOFunction
User-CodeDependent
GPIOPinsasInput(StateDependsonInternalPU/PD)
GPIOPinsasInput
Peripheral/GPIOFunction
t
d(EX)
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013
Table 6-13. Reset (XRS) Timing Requirements
MIN NOM MAX UNIT
t
h(boot-mode)
Hold time for boot-mode pins 1000t
c(SCO)
cycles
t
w(RSL2)
Pulse duration, XRS low on warm reset 32t
c(OSCCLK)
cycles
Table 6-14. Reset (XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
w(RSL1)
Pulse duration, XRS driven by device 600 μs
Pulse duration, reset pulse generated by
t
w(WDRS)
512t
c(OSCCLK)
cycles
watchdog
t
d(EX)
Delay time, address/data valid after XRS high 32t
c(OSCCLK)
cycles
t
INTOSCST
Start up time, internal zero-pin oscillator 3 μs
t
OSCST
(1)
On-chip crystal-oscillator start-up time 1 10 ms
(1) Dependent on crystal/resonator and board design.
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-8. Warm Reset
Copyright © 2008–2013, Texas Instruments Incorporated Electrical Specifications 93
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TMS320F28020 TMS320F280200