Datasheet

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013
Table 6-8. Device Clocking Requirements/Characteristics
MIN NOM MAX UNIT
t
c(OSC)
, Cycle time 50 200 ns
On-chip oscillator (X1/X2 pins)
(Crystal/Resonator)
Frequency 5 20 MHz
t
c(CI)
, Cycle time (C8) 33.3 200 ns
External oscillator/clock source
(XCLKIN pin) — PLL Enabled
Frequency 5 30 MHz
t
c(CI)
, Cycle time (C8) 33.33 250 ns
External oscillator/clock source
(XCLKIN pin) — PLL Disabled
Frequency 4 30 MHz
Limp mode SYSCLKOUT
Frequency range 1 to 5 MHz
(with /2 enabled)
t
c(XCO)
, Cycle time (C1) 66.67 2000 ns
XCLKOUT
Frequency 0.5 15 MHz
PLL lock time
(1)
t
p
1 ms
(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are
used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).
Copyright © 2008–2013, Texas Instruments Incorporated Electrical Specifications 89
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Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021
TMS320F28020 TMS320F280200