Datasheet
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013
www.ti.com
Table 6-2. TMS320F2802x Current Consumption at 50-MHz SYSCLKOUT
VREG ENABLED VREG DISABLED
MODE TEST CONDITIONS I
DDIO
(1)
I
DDA
(2)
I
DD
I
DDIO
(1)
I
DDA
(2)
TYP
(3)
MAX TYP
(3)
MAX TYP
(3)
MAX TYP
(3)
MAX TYP
(3)
MAX
The following peripheral clocks are
enabled:
• ePWM1/2/3/4
• eCAP1
• SCI-A
• SPI-A
• ADC
Operational
80 mA 90 mA 13 mA 18 mA 71 mA 80 mA 15 mA 18 mA 13 mA 18 mA
(Flash)
• I
2
C
• COMP1/2
• CPU Timer0/1/2
All PWM pins are toggled at 40 kHz.
All I/O pins are left unconnected.
(4)
Code is running out of flash with 1 wait-
state.
XCLKOUT is turned off.
Flash is powered down.
IDLE XCLKOUT is turned off. 16 mA 19 mA 64 μA 69 μA 17 mA 20 mA 120 μA 400 μA 64 μA 69 μA
All peripheral clocks are off.
Flash is powered down.
STANDBY 4 mA 7 mA 10 μA 15 μA 4 mA 7 mA 120 μA 400 μA 10 μA 15 μA
Peripheral clocks are off.
Flash is powered down.
HALT Peripheral clocks are off. 50 μA 10 μA 15 μA 15 μA 25 μA 10 μA 15 μA
Input clock is disabled.
(5)
(1) I
DDIO
current is dependent on the electrical loading on the I/O pins.
(2) In order to realize the I
DDA
currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by
writing to the PCLKCR0 register.
(3) The TYP numbers are applicable over room temperature and nominal voltage.
(4) The following is done in a loop:
• Data is continuously transmitted out of SPI-A and SCI-A ports.
• The hardware multiplier is exercised.
• Watchdog is reset.
• ADC is performing continuous conversion.
• COMP1/2 are continuously switching voltages.
• GPIO17 is toggled.
(5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.
82 Electrical Specifications Copyright © 2008–2013, Texas Instruments Incorporated
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TMS320F28020 TMS320F280200