Datasheet

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
SPRS523J –NOVEMBER 2008–REVISED OCTOBER 2013 www.ti.com
6.3 Electrical Characteristics
(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
OH
= I
OH
MAX 2.4
V
OH
High-level output voltage V
I
OH
= 50 μA V
DDIO
– 0.2
V
OL
Low-level output voltage I
OL
= I
OL
MAX 0.4 V
All GPIO –80 –140 –205
Pin with pullup
V
DDIO
= 3.3 V, V
IN
= 0 V
enabled
Input current XRS pin –225 –290 –360
I
IL
μA
(low level)
Pin with pulldown
V
DDIO
= 3.3 V, V
IN
= 0 V ±2
enabled
Pin with pullup
V
DDIO
= 3.3 V, V
IN
= V
DDIO
±2
enabled
Input current
I
IH
μA
(high level)
Pin with pulldown
V
DDIO
= 3.3 V, V
IN
= V
DDIO
28 50 80
enabled
Output current, pullup or
I
OZ
V
O
= V
DDIO
or 0 V ±2 μA
pulldown disabled
C
I
Input capacitance 2 pF
V
DDIO
BOR trip point Falling V
DDIO
2.42 2.65 3.135 V
V
DDIO
BOR hysteresis 35 mV
Supervisor reset release delay Time after BOR/POR/OVR event is removed to XRS
400 800 μs
time release
VREG V
DD
output Internal VREG on 1.9 V
(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage
(V
DD
) go out of range.
80 Electrical Specifications Copyright © 2008–2013, Texas Instruments Incorporated
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TMS320F28020 TMS320F280200